FinFET formation with late fin reveal

Patent metadata

Field	Value
Publication number	US-9171935-B2
Application number	US-201414200104-A
Country	US
Kind code	B2
Filing date	Mar 7, 2014
Priority date	Mar 7, 2014
Publication date	Oct 27, 2015
Grant date	Oct 27, 2015

Abstract

A FinFET semiconductor device fabrication process includes forming a plurality of FinFET fins upon a semiconductor substrate, forming a first dielectric layer upon the semiconductor substrate so that an upper surface of the first dielectric layer is coplanar with upper surfaces of the FinFET fins, forming a plurality of dummy gates upon the FinFET fins and the first dielectric layer orthogonal to the FinFET fins, revealing the FinFET fins by removing first portions of the first dielectric layer from source-drain regions, removing the dummy gates, and subsequent to the removal of the dummy gates, revealing the FinFET fins by removing second portions of the first dielectric layer from channel regions.

First claim

The invention claimed is:

1. A FinFET semiconductor device fabrication process comprising:
forming a plurality of FinFET fins upon a semiconductor substrate;
forming a first dielectric layer upon the semiconductor substrate, an upper surface of the first dielectric layer being coplanar with upper surfaces of the FinFET fins;
forming a plurality of dummy gates upon the FinFET fins and the first dielectric layer orthogonal to the FinFET fins;
revealing first segments of the FinFET fins by removing first portions of the first dielectric layer covering the FinFET fins in source-drain regions adjacent to respective dummy gates;
subsequent to revealing first segments of the FinFET fins, removing the dummy gates, and;
subsequent to the removal of the dummy gates, revealing second segments of the FinFET fins by removing second portions of the first dielectric layer covering the FinFET fins in channel regions.

2. The FinFET semiconductor device fabrication process of claim 1 , wherein forming the first dielectric layer upon the semiconductor substrate comprises:
depositing the first dielectric layer upon the semiconductor substrate covering the FinFET fins, and;
planarizing the first dielectric layer so that the upper surface of the first dielectric layer is coplanar with the upper surfaces of the FinFET fins.

3. The FinFET semiconductor device fabrication process of claim 2 , further comprising:
forming a gate oxide layer upon the upper surface of the first dielectric layer and the upper surface of the plurality of FinFET fins.

4. The FinFET semiconductor device fabrication process of claim 3 , wherein forming the plurality of dummy gates upon the semiconductor substrate comprises:
forming dummy gate material upon the gate oxide layer, and;
patterning the plurality of dummy gates from the dummy gate material.

5. The FinFET semiconductor device fabrication process of claim 4 , further comprising:
forming gate spacers adjacent to sidewalls of the plurality of dummy gates.

6. The FinFET semiconductor device fabrication process of claim 5 , further comprising:
recessing the plurality of FinFET fins to create fin segments, and;
growing epitaxy within the recesses to merge the fin segments.

7. The FinFET semiconductor device fabrication process of claim 6 , further comprising:
subsequent to revealing the first segments of the FinFET fins by removing first portions of the dielectric layer from source-drain regions, depositing a second dielectric layer upon the first dielectric layer covering the revealed first portions of the FinFET fins and the dummy gates, and;
planarizing the second dielectric layer so that an upper surface of the second dielectric layer is coplanar with upper surfaces of the dummy gates.

8. The FinFET semiconductor device fabrication process of claim 3 , wherein the gate oxide layer associated with each dummy gate is retained subsequent to removing the dummy gates.

9. The FinFET semiconductor device fabrication process of claim 1 , wherein the semiconductor substrate is a bulk semiconductor substrate.

10. The FinFET semiconductor device fabrication process of claim 1 , wherein the semiconductor substrate is a silicon-on-insulator semiconductor substrate.

11. A FinFET semiconductor device fabrication process comprising:
forming a plurality of FinFET fins upon a semiconductor substrate;
forming a first dielectric layer upon the semiconductor substrate, an upper surface of the first dielectric layer being coplanar with upper surfaces of the FinFET fins;
forming a plurality of dummy gates upon the FinFET fins and the first dielectric layer orthogonal to the FinFET fins;
revealing first segments of the FinFET fins by removing first portions of the first dielectric layer covering the FinFET fins in source-drain regions adjacent to respective dummy gates;
subsequent to revealing first segments of the FinFET fins, removing the dummy gates resulting in a plurality of channel region trenches, and;
subsequent to the removal of the dummy gates, revealing second segments of the FinFET fins by removing second portions of the first dielectric layer covering the FinFET fins in channel regions accessible via the channel region trenches.

12. The FinFET semiconductor device fabrication process of claim 11 , further comprising:
subsequent to revealing the second segments of the FinFET fins by removing second portions of the dielectric layer from channel regions, forming replacement gates within the channel region trenches.

13. The FinFET semiconductor device fabrication process of claim 12 , wherein forming replacement gates within the channel region trenches comprises:
forming a gate oxide layer upon the retained dielectric layer and the recessed plurality of FinFET fins;
forming gate material upon the gate oxide layer, and;
forming a gate cap upon the gate material.

14. The FinFET semiconductor device fabrication process of claim 12 , further comprising:
subsequent to revealing the first segments of the FinFET fins by removing first portions of the dielectric layer from source-drain regions, depositing a second dielectric layer upon the first dielectric layer covering the revealed first portions of the FinFET fins;
planarizing the replacement gates so that upper surfaces of the replacement gates is coplanar with the top surface of the second dielectric layer.

15. The FinFET semiconductor device fabrication process of claim 11 , wherein upper surfaces of the first portions of the first dielectric layer are coplanar with upper surfaces of the second portions of the first dielectric layer.

16. The FinFET semiconductor device fabrication process of claim 11 , wherein the removal of the first portions of the first dielectric layer from source-drain regions and the removal of the second portions of the first dielectric layer from channel regions results in a retained dielectric layer surrounding the FinFET fins.

17. The FinFET semiconductor device fabrication process of claim 16 , wherein an upper surface of the retained dielectric layer is below the upper surfaces of the FinFET fins.

18. The FinFET semiconductor device fabrication process of claim 11 ,
subsequent to revealing the FinFET fins by removing second portions of the dielectric layer from channel regions, forming spacers adjacent to sidewalls of the channel region trenches.

19. A FinFET semiconductor device fabrication process comprising:
forming a plurality of FinFET fins upon a semiconductor substrate;
forming a first dielectric layer upon the semiconductor substrate, an upper surface of the first dielectric layer being coplanar with upper surfaces of the FinFET fins;
forming a plurality of dummy gates upon the FinFET fins and the first dielectric layer orthogonal to the FinFET fins;
revealing first segments of the FinFET fins by removing first portions of the first dielectric layer covering the FinFET fins in source-drain regions;
subsequent to revealing the first segments of the FinFET fins, depositing a second dielectric layer upon the first dielectric layer covering the revealed first portions of the FinFET fins;
removing the dummy gates resulting in a plurality of channel region trenches;
subsequent to the removal of the dummy gates, revealing second segments of the FinFET fins by removing second portions of the first dielectric layer covering the FinFET fins in channel regions;
subsequent to revealing the second segments of the FinFET fins by removing second portions of the dielectric layer from channel regions adjacent to the FinFE

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Kim Seong-Dong
• Na Myung-Hee
• Wallner Jin Z
• Wallner Thomas A
• Zhang Qintao

Classifications

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H01L29/6681 Primary

  Electricity · mapped topic