Gate structure

Patent metadata

Field	Value
Publication number	US-9171920-B2
Application number	US-201414180714-A
Country	US
Kind code	B2
Filing date	Feb 14, 2014
Priority date	Feb 14, 2014
Publication date	Oct 27, 2015
Grant date	Oct 27, 2015

Abstract

The present invention discloses a gate structure, which is applied for an electronic component comprising a substrate and an active region defined thereon, and such the gate structure is disposed in the active region and is a T-shaped gate having a stem with a height of 250 nm. Preferably, the gate structure has a gate length of 60 nm.

First claim

What is claimed is:

1. A T-shaped gate structure applied for an electronic component, comprising:
a substrate, the substrate is selected from the group consisting of a gallium arsenide (GaAs) substrate and an indium phosphorous (InP) substrate;
an active region defined thereon; and
a T-shaped gate structure is disposed in the active region, and the T-shaped gate having a stem with a height of 250 nm, the T-shaped gate structure has a gate length of 60 nm, a distance between the stem and a sidewall of a recess is 70 nm.

2. The T-shaped gate structure according to claim 1 , wherein the gate structure is formed by the following steps, comprising;
forming and thickening a layer of a first photoresist on the substrate, wherein the step of forming and thickening the layer of the first photoresist is performed by reducing a rotation rate of a spin coating process;
forming a layer of a second photoresist and a layer of a third photoresist in order on the layer of the first photoresist;
patterning the layer of the first photoresist, the layer of the second photoresist and the layer of the third photoresist to form a recess;
depositing a conductive material in the recess; and
removing the layer of the first photoresist, the layer of the second photoresist and the layer of the third photoresist, wherein the step of patterning the layer of the first photoresist, the layer of the second photoresist and the layer of the third photoresist to form a recess is performed by an electron-beam lithography method.

Assignees

• Univ Nat Chiao Tung

Inventors

• Chang Yi
• Kuo Chien-I
• Hsu Heng-Tung

Classifications

• H10D64/0125

  characterised by the sectional shape, e.g. T or inverted T · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10D64/511

  for IGFETs · CPC title

• H10D30/4735

  having delta-doped or planar-doped donor layers · CPC title

• H10D30/47

  having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT] · CPC title