Time varying data permutation apparatus and methods
US-2020145027-A1 · May 7, 2020 · US
Data processing method
US9130593B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9130593-B2 |
| Application number | US-201414310878-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 20, 2014 |
| Priority date | Jul 3, 2009 |
| Publication date | Sep 8, 2015 |
| Grant date | Sep 8, 2015 |
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Abstract
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A data receiving circuit includes: a first de-interleave circuit configured to de-interleave first data which is demodulated and is soft-decision-processed; a second de-interleave circuit configured to de-interleave second data which is demodulated and is soft-decision-processed; a memory configured to be shared by the first de-interleave circuit and the second de-interleave circuit and store respective hard decision information and respective soft decision information of the first data and the second data; and a memory control circuit configured to vary a first through fourth number of bits stored in the memory, the first number corresponding to the hard decision information of the first data, the second number corresponding to the soft decision information of the first data, the third number corresponding to the hard decision information of the second data, the fourth number corresponding to the soft decision information of the second data.
First claim
Opening claim text (preview).
The invention claimed is: 1. A data processing method comprising: de-interleaving a first data which is demodulated and is soft-decision-processed using a first number of bits; de-interleaving a second data which is demodulated and is soft-decision-processed using a second number of bits; reducing at least one of a first soft-decision number of bits for a first Viterbi decoding corresponding to the first data and a second soft-decision number of bits for a second Viterbi decod…
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Electricity · mapped topic
Electricity · mapped topic
- H03M13/2782Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9130593B2 cover?
- A data receiving circuit includes: a first de-interleave circuit configured to de-interleave first data which is demodulated and is soft-decision-processed; a second de-interleave circuit configured to de-interleave second data which is demodulated and is soft-decision-processed; a memory configured to be shared by the first de-interleave circuit and the second de-interleave circuit and store r…
- Who is the assignee on this patent?
- Fujitsu Semiconductor Ltd, Socionext Inc
- What technology area does this patent fall under?
- Primary CPC classification H03M13/2782. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 08 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).