Semiconductor constructions and methods of forming memory cells

Patent metadata

Field	Value
Publication number	US-9166159-B2
Application number	US-201313901195-A
Country	US
Kind code	B2
Filing date	May 23, 2013
Priority date	May 23, 2013
Publication date	Oct 20, 2015
Grant date	Oct 20, 2015

Abstract

Some embodiments include semiconductor constructions having stacks containing electrically conductive material over dielectric material. Programmable material structures are directly against both the electrically conductive material and the dielectric material along sidewall surfaces of the stacks. Electrode material electrically coupled with the electrically conductive material of the stacks. Some embodiments include methods of forming memory cells in which a programmable material plate is formed along a sidewall surface of a stack containing electrically conductive material and dielectric material.

First claim

We claim:

1. A semiconductor construction, comprising:
spaced-apart electrical nodes supported by a semiconductor substrate, upper surfaces of the nodes forming a two-dimensional array having rows and columns, with the columns being substantially orthogonal to the rows; nodes within a common row as one another being coupled to one another through wordlines under the rows;
bridging structures over the nodes and bridging pairs of nodes to one another; the bridging structures exten…

Assignees

• Micron Technology Inc

Inventors

• Cupeta Carmela
• Redaelli Andrea
• Cappelletti Paolo Giuseppe

Classifications

• H10D62/00

  Electricity · mapped topic

• H01L27/2463

  Electricity · mapped topic

• H01L45/1253 Primary

  Electricity · mapped topic

• H01L45/1691

  Electricity · mapped topic

• H01L29/02

  Electricity · mapped topic