Semiconductor package having etched foil capacitor integrated into leadframe

Patent metadata

Field	Value
Publication number	US-9165873-B1
Application number	US-201414494916-A
Country	US
Kind code	B1
Filing date	Sep 24, 2014
Priority date	Jul 28, 2014
Publication date	Oct 20, 2015
Grant date	Oct 20, 2015

Abstract

A packaged semiconductor device including a leadframe made of a first metal, the leadframe including structures with surfaces and sidewalls; capacitors attached to surface portions of the leadframe structures, the capacitors having sidewalls coplanar with structure sidewalls; the capacitors including a foil of conductive material attached to the structure surface, the conductive material having pores covered by oxide and filled with conductive polymer, the capacitors topped by electrodes made of a second metal.

First claim

We claim:

1. A packaged semiconductor device comprising:
a leadframe made of a first metal, the leadframe having structures with surfaces and sidewalls; and
capacitors attached to surface portions of the leadframe structures, the capacitors comprising:
sidewalls coplanar with structure sidewalls;
a conductive material attached to a structure surface, the conductive material having pores covered by oxide and filled with conductive polymer; and
an electrode top made of a second metal.

2. The device of claim 1 wherein the conductive material is a foil.

3. The device of claim 1 wherein the leadframe structures include a chip pad and a plurality of leads.

4. The device of claim 1 wherein the conductive material is selected from a group comprising aluminum, tin, doped silicon, and doped germanium.

5. The device of claim 1 wherein the first metal is selected from a group comprising copper, copper alloys, aluminum, and iron-nickel alloys.

6. The device of claim 1 wherein the second metal is selected from a group comprising silver, copper, and alloys thereof.

7. The device of claim 1 further including a semiconductor chip having bond pads, metal wires connecting the bond pads to leadframe leads, and a packaging compound encapsulating the chip, the wires, the capacitors, and portions of the leads.

8. A leadframe comprising:
a first metal;
a plurality of structures with surface portions and sidewalls; and
a conductive material having a plurality of pores are attached to surface portions of the structures, the plurality of pores including a plurality of surfaces inside of the pores are covered by oxide and filled with conductive polymer, the pores having sidewalls coplanar with structure sidewalls;
the pores topped by an electrode made of a second metal.

9. The device of claim 8 wherein the conductive material is a foil.

10. The device of claim 8 wherein the structures include a chip pad and a plurality of leads.

11. The device of claim 9 wherein the foil is selected from a group comprising aluminum, tin, doped silicon, and doped germanium.

12. The device of claim 8 wherein the first metal is selected from a group comprising copper, copper alloys, aluminum, and iron-nickel alloys.

13. The device of claim 9 wherein the second metal is selected from a group comprising silver, copper, and alloys thereof.

14. The device of claim 9 further including a semiconductor chip having bond pads, metal wires connecting the bond pads to a plurality of leads, and a packaging compound encapsulating the chip, the wires, the capacitors, and portions of the leads.

Assignees

• Texas Instruments Inc

Inventors

• Howard Gregory E
• Gallegos Bernardo
• Dunne Rajiv
• Edwards Darvin R
• Gurrum Siva P
• Prakuzhy Manu J
• Abbott Donald C

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W76/17

  characterised by their materials · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/07554

  changes in dispositions · CPC title