Wake up bias circuit and method of using the same

Patent metadata

Field	Value
Publication number	US-9164522-B2
Application number	US-201314051681-A
Country	US
Kind code	B2
Filing date	Oct 11, 2013
Priority date	Oct 11, 2013
Publication date	Oct 20, 2015
Grant date	Oct 20, 2015

Abstract

A wake up circuit includes a bias signal control block configured to receive a sleep signal and to generate a plurality of bias control signals. The wake up circuit further includes a bias supply block configured to receive each bias control signal of the plurality of bias control signals and to generate a header bias signal. The bias supply block includes a first bias stage configured to receive a first bias control signal of the plurality of bias control signals, and to control the header bias signal to be equal to a first voltage. The bias supply block further includes a second bias stage configured to receive a second bias control signal of the plurality of bias control signals, and to control the header bias signal to be equal to a second voltage different from the first voltage. The wake up circuit further includes a header configured to receive the header bias signal, and to selectively connect a supply voltage to a load based on the header bias signal.

First claim

What is claimed is:

1. A wake up bias circuit comprising:
a bias signal control block configured to receive a sleep signal and to generate a plurality of bias control signals;
a bias supply block configured to receive each bias control signal of the plurality of bias control signals and to generate a header bias signal, the bias supply block comprising:
a first bias stage configured to receive a first bias control signal of the plurality of bias control signals, and to control the header bias signal to be equal to a first voltage,
a second bias stage configured to receive a second bias control signal of the plurality of bias control signals, and to control the header bias signal to be equal to a second voltage different from the first voltage, wherein the second bias stage comprises a transistor having a first type, and
a third bias stage configured to receive a third bias control signal of the plurality of bias control signals, and to control the header bias signal to be equal to a third voltage different from the first voltage and from the second voltage, wherein the third bias stage comprises a transistor having a second type opposite the first type; and

a header configured to receive the header bias signal, and to selectively connect a supply voltage to a load based on the header bias signal.

2. The wake up bias circuit of claim 1 , wherein the bias signal control block comprises:
a first bias signal generator configured to receive the sleep signal, and to output the first bias control signal of the plurality of bias control signals; and
a second bias signal generator configured to output the second bias control signal of the plurality of bias control signals.

3. The wake up circuit of claim 2 , wherein the first bias signal generator is configure to output a first delayed signal, wherein the first delayed signal is delayed by a first duration with respect to the sleep signal, and
the second bias signal generator is configured to receive the first delayed signal.

4. The wake up circuit of claim 3 , wherein the bias signal control block further comprises a third bias signal generator, the first bias signal generator is configure to output a second delayed signal, the second delayed signal is delayed by a second duration with respect to the first delayed signal,
the third bias signal generator is configured to receive the second delayed signal, and
the first duration is equal to the second duration.

5. The wake up circuit of claim 1 , wherein the first voltage is greater than the second voltage.

6. The wake up circuit of claim 1 , wherein the header comprises a header transistor having a gate configured to receive the header bias signal.

7. A wake up bias circuit comprising:
a bias signal control block, the bias signal control block comprising:
a first bias signal generator configured to receive a sleep signal and to output a first bias control signal and a first delayed signal,
a second bias signal generator configured to receive the first delayed signal and to generate a second bias control signal, wherein the first delayed signal is delayed by a first duration with respect to the sleep signal, and
a third bias signal generator configured to receive a second delayed signal and to generate a third bias control signal, wherein the second delayed signal is delayed by a second duration with respect to the first delayed signal;

a bias supply block configured to receive the first bias control signal, the second bias control signal and the third bias control signal, and to generate a header bias signal; and
a header configured to receive the header bias signal, and to selectively connect a supply voltage to a load based on the header bias signal.

8. The wake up circuit of claim 7 , wherein the first bias signal generator comprises:
a first delay circuit configured to receive an inverted sleep signal and to output the first delayed signal;
a second delay circuit configured to receive the first delayed signal and to output the second delayed signal;
an inverter configured to receive the second delayed signal and to output a first inverter signal; and
a NAND gate configured to receive the inverted sleep signal and the first inverter signal, and to output the first bias control signal.

9. The wake up circuit of claim 7 , wherein the second bias signal generator comprises:
an inverter configured to receive the first delayed signal and to output a second inverter signal; and
a NAND gate configured to receive an inverted sleep signal and the second inverter signal, and to output the second bias control signal.

10. The wake up circuit of claim 7 , wherein the third bias signal generator comprises an AND gate configured to receive the second delayed signal and an inverted sleep signal, and to output the third bias control signal.

11. The wake up circuit of claim 7 , wherein the bias supply block comprises:
a first bias stage configured to receive the first bias control signal, and to control the header bias signal to be equal to a first voltage,
a second bias stage configured to receive the second bias control signal, and to control the header bias signal to be equal to a second voltage different from the first voltage, and
a third bias stage configured to receive the third bias control signal, and to control the header bias signal to be equal to a third voltage different from the first voltage and the second voltage.

12. The wake up circuit of claim 11 , wherein the first bias stage comprises:
a first transistor having a first gate configured to receive the first bias control signal, a first terminal configured to receive the supply voltage; and
a second transistor having a second gate configured to receive the first bias control signal, a first terminal configured to receive a ground voltage, wherein a second terminal of the first transistor is connected to a second terminal of the second transistor.

13. The wake up circuit of claim 12 , wherein the second bias stage comprises a third transistor having a gate configured to receive the second bias control signal, a first terminal configured to receive the ground voltage and a second terminal connected to the second terminal of the first transistor.

14. The wake up circuit of claim 12 , wherein the third bias stage comprises a fourth transistor having a gate configured to receive the third bias control signal, a first terminal configured to receive the ground voltage and a second terminal connected to the second terminal of the first transistor.

15. The wake up circuit of claim 12 , wherein the header comprises a header transistor having a gate connected to the second terminal of the first transistor, a first terminal configured to receive the supply voltage and a second terminal connected to the load.

16. A method of using a wake up bias circuit, the method comprising:
receiving a sleep signal;
generating a plurality of bias control signals using a bias signal control block;
generating a first delayed signal using a first bias signal generator;
controlling a header bias based on each bias control signal of the plurality of bias control signals using a bias supply block, wherein controlling the header bias comprises:
controlling the header bias to be equal to a first voltage using a first bias stage receiving a first bias control signal of the plurality of bias control signals,
controlling the header bias to be equal to a second voltage different from the first voltage using a second bias stage receiving a second bias control signal of the plurality of bias control signals, and
controlling the header bias to be

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Yang Jung-Ping
• Huang I-Han
• Huang Chia-En
• Wu Fu-An
• Chiu Chih-Chieh

Classifications

• G05F1/46 Primary

  wherein the variable actually regulated by the final control device is DC (G05F1/625 takes precedence) · CPC title

• H03K17/163 Primary

  Soft switching · CPC title

• H03K17/164

  using parallel switching arrangements · CPC title