Printed wiring board and method for manufacturing printed wiring board

Patent metadata

Field	Value
Publication number	US-9161445-B2
Application number	US-201313930733-A
Country	US
Kind code	B2
Filing date	Jun 28, 2013
Priority date	Dec 18, 2009
Publication date	Oct 13, 2015
Grant date	Oct 13, 2015

Abstract

A printed wiring board includes a resin layer, pads formed on the resin layer and positioned to be connected to an electronic component, and a solder-resist layer formed on the resin layer and exposing upper surfaces of the pads and portions of side walls of the pads. Each of the pads has a metal layer such that the metal layer is formed on each of the upper surfaces of the pads and each of the portions of the side walls of the pads exposed by the solder-resist layer.

First claim

What is claimed is:

1. A printed wiring board, comprising:
a resin layer;
a plurality of pads formed on the resin layer and positioned to be connected to an electronic component; and
a solder-resist layer formed on the resin layer and exposing upper surfaces of the pads and portions of side walls of the pads,
wherein each of the pads has a metal layer such that the metal layer is formed on each of the upper surfaces of the pads and each of the portions of the side walls of the pads exposed by the solder-resist layer, and the plurality of pads is positioned such that the electronic component is wire-bonded to the pads.

2. The printed wiring board according to claim 1 , wherein a portion of the solder-resist layer between the pads has a thickness which is less than a thickness of the pads.

3. The printed wiring board according to claim 2 , further comprising:
a plurality of solder pads formed on the resin layer; and
a plurality of conductive circuits formed on the resin layer,
wherein the solder-resist layer is covering outer periphery portions of the solder pads and has openings exposing the upper surfaces of the solder pads, and the portion of the solder-resist layer formed between the pads has a thickness which is less than a thickness of a portion of the solder-resist layer between the solder pads.

4. The printed wiring board according to claim 3 , wherein the metal layer includes a nickel layer formed on each of the pads and solder pads and a gold layer formed on the nickel layer.

5. The printed wiring board according to claim 3 , wherein the metal layer includes a nickel layer formed on each of the pads and solder pads, a palladium layer formed on the nickel layer and a gold layer formed on the palladium layer.

6. The printed wiring board according to claim 3 , wherein each of the pads includes an electroless plated film on the resin layer and an electrolytic plated film on the electroless plated film, and the metal layer includes a nickel layer formed on each of the pads and solder pads and a gold layer formed on the nickel layer.

7. The printed wiring board according to claim 3 , wherein each of the pads includes an electroless plated film on the resin layer and an electrolytic plated film on the electroless plated film, and the metal layer includes a nickel layer formed on each of the pads and solder pads, a palladium layer formed on the nickel layer and a gold layer formed on the palladium layer.

8. The printed wiring board according to claim 2 , further comprising:
a conductive circuit formed on the resin layer; and
a solder pad formed on the resin layer,
wherein the solder-resist layer is formed on the conductive circuit and the solder pad.

9. The printed wiring board according to claim 1 , wherein each of the pads includes a catalyst on the resin layer, an electroless plated film on the resin layer and an electrolytic plated film on the electroless plated film.

10. The printed wiring board according to claim 9 , wherein the catalyst is palladium.

11. The printed wiring board according to claim 1 , wherein the metal layer includes a nickel layer formed on each of the pads and a gold layer formed on the nickel layer.

12. The printed wiring board according to claim 1 , wherein the metal layer includes a nickel layer formed on each of the pads, a palladium layer formed on the nickel layer, and a gold layer formed on the palladium layer.

13. The printed wiring board according to claim 1 , wherein the metal layer includes a tin layer.

14. The printed wiring board according to claim 1 , further comprising:
a conductive circuit formed on the resin layer; and
a solder pad formed on the resin layer,
wherein the solder-resist layer is formed on the conductive circuit and the solder pad.

15. The printed wiring board according to claim 14 , wherein the solder-resist layer has an opening exposing the solder pad, and the metal layer is formed on a portion of the solder pad exposed through the opening of the solder-resist layer.

16. The printed wiring board according to claim 14 , further comprising a solder bump formed on the solder pad configured to flip-chip mount the electronic component.

17. The printed wiring board according to claim 16 , wherein the solder-resist layer is covering an outer periphery portion of the solder pad.

18. The printed wiring board according to claim 1 , wherein each of the pads includes an electroless plated film on the resin layer and an electrolytic plated film on the electroless plated film, and the metal layer includes a nickel layer formed on each of the pads, a palladium layer formed on the nickel layer, and a gold layer formed on the palladium layer.

19. The printed wiring board according to claim 1 , wherein each of the pads includes an electroless plated film on the resin layer and an electrolytic plated film on the electroless plated film, and the metal layer includes a tin layer.

20. The printed wiring board according to claim 1 , wherein each of the pads includes an electroless plated film on the resin layer and an electrolytic plated film on the electroless plated film, and the metal layer includes a nickel layer formed on each of the pads, a palladium layer formed on the nickel layer, and a gold layer formed on the palladium layer.

Assignees

• Ibiden Co Ltd

Inventors

• Takada Masaru
• Nagaya Fusaji
• Okada Takao
• Murata Tomohiko

Classifications

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title