Efficient, programmable and scalable low density parity check decoder

US9160366B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9160366-B2
Application numberUS-201314070000-A
CountryUS
Kind codeB2
Filing dateNov 1, 2013
Priority dateMar 31, 2008
Publication dateOct 13, 2015
Grant dateOct 13, 2015

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Abstract

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Novel design of an LDPC decoder suitable for a range of code-block sizes and bit-rates, also suitable for both ASIC and FPGA implementations, is provided, in which the overhead associated with correction data sent along the transmission channel can be minimized. An LDPC decoder can be optimized for either eIRA based or general H matrices. An H parity matrix can be constructed and/or manipulated to arrange the bit-node message “columns” to facilitate mapping to MPB “columns” and corresponding access via LUT pointer tables to minimize processing cycles so as to: (i) minimize address conflicts within the same MPB that will take multiple access cycles to resolve; (ii) minimize splitting of bit-node messages across MPB “columns” that will take multiple access cycles to resolve; and (iii) balance the bit-node computations across all the MPB/LUT “columns” so that they will complete their computations at nearly the same time.

First claim

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What is claimed: 1. A low density parity check decoder comprising: a plurality of message processing blocks arranged in a logical array; a plurality of info bit processors, one for each column of said message processing blocks in said logical array; a plurality of lookup table memories, one for each column of said message processing blocks in said logical array; and a plurality of check message processors, one for each row of said message processing blocks in said logical arra…

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What does patent US9160366B2 cover?
Novel design of an LDPC decoder suitable for a range of code-block sizes and bit-rates, also suitable for both ASIC and FPGA implementations, is provided, in which the overhead associated with correction data sent along the transmission channel can be minimized. An LDPC decoder can be optimized for either eIRA based or general H matrices. An H parity matrix can be constructed and/or manipulated…
Who is the assignee on this patent?
Sirius Xm Radio Inc
What technology area does this patent fall under?
Primary CPC classification H03M13/1137. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 13 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).