Ultra fine pitch and spacing interconnects for substrate

Patent metadata

Field	Value
Publication number	US-9159670-B2
Application number	US-201414318490-A
Country	US
Kind code	B2
Filing date	Jun 27, 2014
Priority date	Aug 29, 2013
Publication date	Oct 13, 2015
Grant date	Oct 13, 2015

Abstract

Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a second interconnect. The first dielectric layer includes first and second surfaces. The first interconnect is embedded in the first dielectric layer. The first interconnect includes a first side and a second side. The first side is surrounded by the first dielectric layer, where at least a part of the second side is free of contact with the first dielectric layer. The first cavity traverses the first surface of the first dielectric layer to the second side of the first interconnect, where the first cavity overlaps the first interconnect. The second interconnect includes a third side and a fourth side, where the third side is coupled to the first surface of the first dielectric layer.

First claim

What is claimed is:

1. A substrate comprising:
a first dielectric layer comprising a first surface and a second surface;
a first interconnect embedded in the first dielectric layer, the first interconnect comprising a first side and a second side, the first side is surrounded by the first dielectric layer, wherein at least a part of the second side is free of contact with the first dielectric layer, wherein the first interconnect is a first trace;
a first cavity traversing the first surface of the first dielectric layer to the second side of the first interconnect, wherein the first cavity overlaps the first interconnect; and
a second interconnect comprising a third side and a fourth side, wherein the third side is at least partially coupled onto the first surface of the first dielectric layer, wherein the second interconnect is a second trace.

2. The substrate of claim 1 , further comprising:
a third interconnect embedded in the first dielectric layer, the third interconnect comprising a fifth side and a sixth side, the fifth side is surrounded by the first dielectric layer, wherein at least a part of the sixth side is free of contact with the first dielectric layer;
a second cavity traversing the first surface of the first dielectric layer to the sixth side of the third interconnect, wherein the second cavity overlaps the third interconnect; and
a fourth interconnect on the first surface of the first dielectric layer, the fourth interconnect comprising a seventh side and an eighth side, wherein the seventh side is coupled to the first surface of the first dielectric layer.

3. The substrate of claim 2 , wherein a lateral spacing between the first interconnect and the third interconnect is about 30 microns (μm) or less.

4. The substrate of claim 1 , wherein a lateral spacing between the first interconnect and the second interconnect is about 10 microns (μm) or less, wherein the first interconnect and the second interconnect are adjacent interconnects.

5. The substrate of claim 1 , further comprising:
a third interconnect on the first surface of the first dielectric layer, the third interconnect coupled to the first interconnect; and
a fourth interconnect on the first surface of the first dielectric layer, the fourth interconnect coupled to the second interconnect.

6. The substrate of claim 5 , wherein the third and fourth interconnects are pads.

7. The substrate of claim 1 , wherein the substrate is a package substrate.

8. The substrate of claim 1 , further comprising a second dielectric layer.

9. The substrate of claim 1 , wherein the substrate is incorporated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer, and further including the device.

10. The substrate of claim 1 further comprising:
a third interconnect embedded in the first dielectric layer; and
a fourth interconnect at least partially on the third interconnect.

11. The substrate of claim 10 , wherein the third interconnect comprises a first cross-sectional dimension, and the fourth interconnect comprises a second cross-sectional dimension that is less than the first cross sectional dimension.

12. The substrate of claim 10 , wherein the fourth interconnect is partially on the third interconnect and partially on the first dielectric layer.

13. The substrate of claim 10 , wherein the fourth interconnect is a pad.

14. The substrate of claim 10 , wherein the third interconnect is coupled to the first interconnect.

15. The substrate of claim 1 , further comprising a third interconnect on the first dielectric layer.

16. The substrate of claim 15 , wherein the third interconnect is a pad.

17. The substrate of claim 1 , further comprising a non-conducting material that at least partially fills the first cavity.

18. A method for fabricating a substrate, comprising:
forming a first dielectric layer comprising a first surface and a second surface;
forming a first interconnect inside the first dielectric layer, wherein forming the first interconnect comprises:
forming a first side of the first interconnect in the first dielectric layer such that the first side is surrounded by the first dielectric layer, wherein the first interconnect is a first trace;
forming a second side of the first interconnect in the first dielectric layer such that at least a part of the second side is free of contact with the first dielectric layer, wherein the second side is formed in the first dielectric layer offset from the first surface of the first dielectric layer such that a first cavity in the first dielectric layer is formed between the first surface of the first dielectric layer and the second side of the first interconnect; and

forming a second interconnect on the first surface of the first dielectric layer, wherein forming the second interconnect comprises:
forming a third side of the second interconnect on the first surface of the first dielectric layer, wherein the second interconnect is a second trace; and
forming a fourth side of the second interconnect outside of the first dielectric layer.

19. The method of claim 18 , further comprising:
forming a third interconnect inside the first dielectric layer, wherein forming the third interconnect comprises:
forming a fifth side of the third interconnect in the first dielectric layer such that the fifth side is surrounded by the first dielectric layer; and
forming a sixth side of the third interconnect in the first dielectric layer such that at least a part of the sixth side is free of contact with the first dielectric layer, wherein the sixth side is formed in the first dielectric layer offset from the first surface of the first dielectric layer such that a second cavity in the first dielectric layer is formed between the first surface of the first dielectric layer and the sixth side of the third interconnect; and

forming a fourth interconnect on the first surface of the first dielectric layer, wherein forming the fourth interconnect comprises:
forming a seventh side of the fourth interconnect on the first surface of the first dielectric layer; and
forming an eighth side of the fourth interconnect outside of the first dielectric layer.

20. The method of claim 19 , wherein a lateral spacing between the first interconnect and the third interconnect is about 30 microns (μm) or less.

21. The method of claim 18 , wherein a lateral spacing between the first interconnect and the second interconnect is about 10 microns (μm) or less, wherein the first interconnect and the second interconnect are adjacent interconnects.

22. The method of claim 18 , further comprising:
forming a third interconnect on the first surface of the first dielectric layer such that the third interconnect is coupled to the first interconnect; and
forming a fourth interconnect on the first surface of the first dielectric layer such that the fourth interconnect is coupled to the second interconnect.

23. The method of claim 22 , wherein the third and fourth interconnects are pads.

24. The method of claim 18 , wherein the substrate is a package substrate.

25. The method of claim 18 , wherein forming the first cavity comprises removing a portion of the first interconnect to form the first c

Assignees

• Qualcomm Inc

Inventors

• Kim Chin-Kwan
• Kumar Rajneesh
• Bchir Omar James

Classifications

• H05K1/0296

  Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295 (H05K1/11 takes precedence; lay-out adapted to mounted component configuration H05K1/18) · CPC title

• H05K1/111

  Pads for surface mounting, e.g. lay-out · CPC title

• H05K2201/0376

  Flush conductors, i.e. flush with the surface of the printed circuit · CPC title

• H05K3/4682

  Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil · CPC title

• H05K2201/094

  Array of pads or lands differing from one another, e.g. in size, pitch or thickness; Using different connections on the pads · CPC title