Method of forming a germanium-containing FinFET

Patent metadata

Field	Value
Publication number	US-9159552-B2
Application number	US-201314142435-A
Country	US
Kind code	B2
Filing date	Dec 27, 2013
Priority date	Dec 27, 2013
Publication date	Oct 13, 2015
Grant date	Oct 13, 2015

Abstract

A method includes forming isolation regions in a semiconductor substrate, forming a first semiconductor strip between opposite portions of isolation regions, forming a second semiconductor strip overlying and contacting the first semiconductor strip, and performing a first recessing to recess the isolation regions. A portion of the second semiconductor strip over top surfaces of remaining portions of the isolation regions forms a semiconductor fin. A second recessing is performed to recess the isolation regions to extend the semiconductor fin downwardly, with an inter-diffusion region of the first semiconductor strip and the second semiconductor strip being exposed after the second recessing. The inter-diffusion region is then etched.

First claim

What is claimed is:

1. A method comprising:
forming isolation regions in a semiconductor substrate;
forming a first semiconductor strip between opposite portions of isolation regions;
forming a second semiconductor strip overlying and contacting the first semiconductor strip;
performing a first recessing to recess the isolation regions, wherein a portion of the second semiconductor strip over top surfaces of remaining portions of the isolation regions forms a semiconductor f…

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Fan Chun-Hsiang
• Lu Kun-Yen
• Huang Yu-Lien
• Tsai Ming-Huan

Classifications

• H10W10/17

  Electricity · mapped topic

• H10W10/014

  Electricity · mapped topic

• H10D64/017

  Electricity · mapped topic

• H10D62/822

  Electricity · mapped topic

• H10D62/116

  Electricity · mapped topic