Silicon based nanoscale crossbar memory

Patent metadata

Field	Value
Publication number	US-9159416-B2
Application number	US-201414563698-A
Country	US
Kind code	B2
Filing date	Dec 8, 2014
Priority date	Oct 20, 2008
Publication date	Oct 13, 2015
Grant date	Oct 13, 2015

Abstract

The present application describes a crossbar memory array. The memory array includes a first array of parallel nanowires of a first material and a second array of parallel nanowires of a second material. The first and the second array are oriented at an angle with each other. The array further includes a plurality of nanostructures of non-crystalline silicon disposed between a nanowire of the first material and a nanowire of the second material at each intersection of the two arrays. The nanostructures form a resistive memory cell together with the nanowires of the first and second materials.

First claim

The invention claimed is:

1. A method for a crossbar memory array having a first plurality of metallic nanowires, a second plurality of metallic nanowires, and a plurality of resistive memory devices electrically disposed between the first plurality of metallic nanowires and the second plurality of metallic nanowires, the method comprising:
applying with a control circuit a voltage to a gate of a first transistor;
coupling a source of the first transistor to a drain of the first transistor in response to the voltage applied to the gate to thereby cause a first voltage to be applied across a first metallic nanowire from the first plurality of metallic nanowires, a second metallic nanowire from the second plurality of metallic nanowires, and a resistive memory device from the plurality of resistive memory devices, wherein the resistive memory device comprises a layer of resistive switching material contacting the first metallic nanowire, and a layer of conductive silicon bearing material having a first surface contacting the layer of resistive switching material and having a second surface contacting the second metallic nanowire;
supplying a plurality of metallic particles from the first metallic nanowire to the layer of resistive switching material in response to the first voltage being applied, wherein metallic particles from the plurality of metallic particles are supplied to a plurality of defect sites within the layer of resistive switching material in response to the first voltage;
removing with the control circuit the voltage from the gate of the first transistor;
decoupling the source of the first transistor to the drain of the first transistor in response to the first voltage being removed from the gate to thereby cause the first voltage to be removed from across the first metallic nanowire, the second metallic nanowire, and the resistive memory device;
wherein the plurality of metallic particles become trapped in the plurality of defect sites within the layer of resistive switching material in response to the first voltage being removed;
wherein the plurality of metallic particles form a conductive filament within the layer of resistive switching material; and
wherein a first resistance of the resistive memory device is characterized by a first tunneling resistance between the layer of conductive silicon bearing material and the conductive filament.

2. The method of claim 1 wherein the plurality of metallic particles comprise particles selected from a group consisting of: silver particles, gold particles, nickel particles, aluminum particles, chromium particles.

3. The method of claim 1 wherein the resistive switching material is selected from a group consisting of: amorphous silicon-bearing material, and non-crystalline silicon-bearing material.

4. The method of claim 1 wherein the conductive silicon bearing material is selected from a group consisting of: a p-type doped polycrystalline silicon-bearing material and a p-type polysilicon.

5. The method of claim 1 further comprising:
applying a second voltage across the first metallic nanowire, the second metallic nanowire, and the resistive memory device to thereby induce a current flow through the resistive memory device, wherein the current flow is dependent upon the first tunneling resistance;
wherein the second voltage is a read voltage; and
wherein metallic particles from the plurality of metallic particles trapped in the plurality of defect sites within the layer of resistive switching material remain trapped while the second voltage is applied across the first metallic nanowire, the resistive memory device, and the second metallic nanowire.

6. The method of claim 1 :
wherein a current flows across the first metallic nanowire, the second metallic nanowire and the resistive memory device in response to the first voltage, and
wherein the current flow is less than about 20 uA.

7. The method of claim 1 wherein the first tunneling resistance is associated with a tunneling resistance between a metallic particle of the conductive filament and the layer of conductive silicon bearing material.

8. The method of claim 1 further comprising:
applying a third voltage across the first metallic nanowire, the second metallic nanowire, and the resistive memory device to thereby cause metallic particles from the plurality of metal particles trapped in the plurality of defect sites within the layer of resistive switching material to migrate in response to the third voltage;
wherein the third voltage is an erase voltage; and
wherein the metallic particles migrate towards the first metallic nanowire.

9. The method of claim 8 wherein the third voltage has an opposite polarity from a polarity of the first voltage.

10. The method of claim 1 further comprising:
selecting the first transistor from a plurality of transistors comprising the first transistor and a second transistor;
wherein the first transistor is associated with the first tunneling resistance for the resistive memory device; and
wherein the second transistor is associated with a second tunneling resistance for the resistive memory device.

11. A method for a crossbar memory array having a first plurality of metallic electrodes, a second plurality of electrodes, and a plurality of resistive memory devices electrically disposed between the first plurality of metallic electrodes and the second plurality of electrodes, the method comprising:
applying with a control circuit a voltage to a gate of a first transistor; and
coupling a source of the first transistor to a drain of the first transistor in response to the voltage applied to the gate to thereby cause a read voltage to be applied across a first metallic electrode from the first plurality of metallic electrodes, a second electrode from the second plurality of electrodes, and a resistive memory device from the plurality of resistive memory devices, and to thereby induce a current flow through the resistive memory device, wherein the current flow is dependent upon a first tunneling resistance of the resistive memory device, wherein the resistive memory device comprises a layer of resistive switching material having a first surface contacting the first metallic electrode and a second surface contacting the second electrode;
wherein metallic particles from a plurality of metallic particles from the first metallic electrode are trapped in a plurality of defect sites within the layer of resistive switching material;
wherein the plurality of metallic particles form a conductive filament within the layer of resistive switching material;
wherein the first tunneling resistance is characterized by a tunneling resistance associated with the conductive filament within the layer of resistive switching material; and
wherein the metallic particles trapped in the plurality of defect sites within the layer of resistive switching material remain trapped while the read voltage is applied across the first metallic electrode, the resistive memory device, and the second metallic electrode.

12. The method of claim 11 wherein the plurality of metallic particles comprise particles selected from a group consisting of: silver particles, gold particles, nickel particles, aluminum particles, chromium particles.

13. The method of claim 11 wherein the resistive switching material is selected from a group consisting of: amorphous silicon-bearing material, and non-crystalline silicon.

14. The method of claim 11 wherein the second plurality of electrodes comprise a conductive silicon bearing material selected from a group consisting of: a p-type doped polycrystalline silicon-bearing ma

Assignees

• Univ Michigan

Inventors

• Lu Wei
• Jo Sung Hyun
• Kim Kuk-Hwan

Classifications

• H01L27/2463

  Electricity · mapped topic

• G11C2213/81

  Array wherein the array conductors, e.g. word lines, bit lines, are made of nanowires · CPC title

• H01L45/148

  Electricity · mapped topic

• G11C2013/0071

  Write using write potential applied to access device gate · CPC title

• H01L45/1675

  Electricity · mapped topic