Inflexible voltage reference circuit card, and method for manufacturing an inflexible voltage reference circuit card
US-2024215166-A1 · Jun 27, 2024 · US
US9155191B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9155191-B2 |
| Application number | US-201313967186-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 14, 2013 |
| Priority date | May 31, 2013 |
| Publication date | Oct 6, 2015 |
| Grant date | Oct 6, 2015 |
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Some novel features pertain to a substrate that includes a first core layer, a second core layer laterally located to the first core layer in the substrate, a first inorganic core layer (e.g., glass, silicon, ceramic) laterally positioned between the first core layer and the second core layer, the first inorganic core layer configured to be vertically aligned with a die configured to be coupled to the substrate, and a dielectric layer covering the first core layer, the second core layer and the first inorganic core layer. In some implementations, the first inorganic core layer has a first coefficient of thermal expansion (CTE), the die has a second coefficient of thermal expansion, and the first core layer has a third coefficient of thermal expansion (CTE). The first CTE of the first inorganic core layer closely matches the second CTE of the die in order to reduce the likelihood of warpage.
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What is claimed is: 1. An integrated device comprising: a substrate including: a first core layer comprising a first Young's Modulus; a second core layer laterally located relative to the first core layer in the substrate; a first inorganic core layer laterally positioned between the first core layer and the second core layer, the first inorganic core layer comprising a second Young's Modulus that is greater than the first Young Modulus, wherein the first inorganic core laye…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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