Semiconductor device, power circuit, and manufacturing method of semiconductor device

Patent metadata

Field	Value
Publication number	US-9153702-B2
Application number	US-201414272545-A
Country	US
Kind code	B2
Filing date	May 8, 2014
Priority date	Sep 24, 2009
Publication date	Oct 6, 2015
Grant date	Oct 6, 2015

Abstract

The semiconductor device includes a first conductive layer over a substrate; an oxide semiconductor layer which covers the first conductive layer; a second conductive layer in a region which is not overlapped with the first conductive layer over the oxide semiconductor layer; an insulating layer which covers the oxide semiconductor layer and the second conductive layer; and a third conductive layer in a region including at least a region which is not overlapped with the first conductive layer or the second conductive layer over the insulating layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first conductive layer over a substrate;
an oxide semiconductor layer over the first conductive layer;
a second conductive layer over the oxide semiconductor layer, wherein the second conductive layer is not overlapped with the first conductive layer;
an insulating layer over the oxide semiconductor layer and the second conductive layer; and
a third conductive layer over the insulating layer, wherein the third conductive layer comprises at least a first portion which is overlapped with neither the first conductive layer nor the second conductive layer,
wherein the first conductive layer serves as one of a source electrode and a drain electrode,
wherein the second conductive layer serves as the other of the source electrode and the drain electrode, and
wherein the third conductive layer serves as a gate electrode.

2. The semiconductor device according to claim 1 , wherein the third conductive layer is located between the first conductive layer and the second conductive layer when seen from above.

3. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer covers the first conductive layer.

4. The semiconductor device according to claim 1 , wherein a part of the first conductive layer is not overlapped with the oxide semiconductor layer.

5. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

6. The semiconductor device according to claim 1 , wherein the third conductive layer comprises a second portion which is overlapped with the second conductive layer.

7. The semiconductor device according to claim 1 , wherein the second conductive layer is surrounded by the third conductive layer when seen from above.

8. A power circuit comprising the semiconductor device according to claim 1 , wherein the power circuit changes output voltage by switching an on state and off state of the semiconductor device in accordance with a pulse signal input to the third conductive layer.

9. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises a crystal region at an upper superficial portion.

10. The semiconductor device according to claim 9 , wherein the crystal region comprises In 2 Ga 2 ZnO 7 crystal.

11. A method for manufacturing a semiconductor device, comprising the steps of:
forming a first conductive layer over a substrate;
forming an oxide semiconductor layer over the first conductive layer;
forming a second conductive layer over the oxide semiconductor layer, wherein the second conductive layer is not overlapped with the first conductive layer;
forming an insulating layer over the oxide semiconductor layer and the second conductive layer; and
forming a third conductive layer over the insulating layer, wherein the third conductive layer comprises at least a first portion which is overlapped with neither the first conductive layer nor the second conductive layer,
wherein the first conductive layer serves as one of a source electrode and a drain electrode,
wherein the second conductive layer serves as the other of the source electrode and the drain electrode, and
wherein the third conductive layer serves as a gate electrode.

12. The method for manufacturing a semiconductor device according to claim 11 , wherein the third conductive layer is located between the first conductive layer and the second conductive layer when seen from above.

13. The method for manufacturing a semiconductor device according to claim 11 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

14. The method for manufacturing a semiconductor device according to claim 11 , wherein the third conductive layer comprises a second portion which is overlapped with the second conductive layer.

15. The method for manufacturing a semiconductor device according to claim 11 , wherein a part of the first conductive layer is not overlapped with the oxide semiconductor layer.

16. The method for manufacturing a semiconductor device according to claim 11 , wherein the second conductive layer is surrounded by the third conductive layer when seen from above.

17. The method for manufacturing a semiconductor device according to claim 11 ,
further comprising the step of forming a crystal region at an upper superficial portion of the oxide semiconductor layer by heating the oxide semiconductor layer,
wherein the second conductive layer is formed over the crystal region.

18. The method for manufacturing a semiconductor device according to claim 17 , wherein the crystal region is formed by heating the oxide semiconductor layer at 500° C. or higher.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Takahashi Kei
• Ito Yoshiaki

Classifications

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/3426

  Oxides · CPC title

• H10P14/2901

  Materials · CPC title

• H10D62/875

  being semiconductor metal oxide, e.g. InGaZnO (Group II-VI materials H10D62/86; Group I-VI materials H10D62/871; Pb compounds or alloys H10D62/874) · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title