Page buffer performing memory operation
US-2024274171-A1 · Aug 15, 2024 · US
Memory and method of operating the same
US9153302B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9153302-B2 |
| Application number | US-201213362847-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 31, 2012 |
| Priority date | Jan 31, 2012 |
| Publication date | Oct 6, 2015 |
| Grant date | Oct 6, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A memory includes a plurality of memory blocks, a plurality of global bit lines, a common pre-charging circuit, and a selection circuit. Each memory block includes a pair of bit lines, and a plurality of memory cells coupled to the pair of bit lines. Each global bit line is coupled to at least one of the memory blocks. The pre-charging circuit is configured to pre-charge the global bit lines, one at a time, to a pre-charge voltage. The selection circuit is coupled between the pre-charging circuit and the global bit lines, and configured to couple the global bit lines, one at a time, to the pre-charging circuit.
First claim
Opening claim text (preview).
What is claimed is: 1. A memory, comprising: a plurality of memory blocks, each memory block comprising: a pair of bit lines, a plurality of memory cells coupled to the pair of bit lines, and a local bit line pre-charging circuit configured to pre-charge the bit lines; a plurality of global bit lines, each global bit line coupled to at least one of the memory blocks; a common pre-charging circuit for the global bit lines, the common pre-charging circuit configured to pr…
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Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G11C7/12Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US9153302B2 cover?
- A memory includes a plurality of memory blocks, a plurality of global bit lines, a common pre-charging circuit, and a selection circuit. Each memory block includes a pair of bit lines, and a plurality of memory cells coupled to the pair of bit lines. Each global bit line is coupled to at least one of the memory blocks. The pre-charging circuit is configured to pre-charge the global bit lines, o…
- Who is the assignee on this patent?
- Yang Jung-Ping, Cheng Hong-Chen, Chiu Chih-Chieh, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification G11C7/12. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Oct 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).