Memory array with a pair of memory-cell strings to a single conductive pillar

Patent metadata

Field	Value
Publication number	US-9147693-B2
Application number	US-201213676407-A
Country	US
Kind code	B2
Filing date	Nov 14, 2012
Priority date	Mar 13, 2008
Publication date	Sep 29, 2015
Grant date	Sep 29, 2015

Abstract

An array of memory cells has a conductive pillar and a plurality of first and second memory cells coupled in series by the conductive pillar. Each first memory cell has a respective portion of a first charge trap adjacent to the conductive pillar and a respective first control gate adjacent to the respective portion of the first charge trap. Each second memory cell has a respective portion of a second charge trap adjacent to the conductive pillar and a respective second control gate adjacent to the respective portion of the second charge trap. Each first control gate is electrically isolated from each second control gate. A single select transistor may selectively couple the plurality of first memory cells and the plurality of second memory cells to one of a source line and a data line.

First claim

What is claimed is:

1. A memory array, comprising:
a substantially vertical conductive pillar;
a plurality of first memory cells on a first side of the substantially vertical conductive pillar coupled in series by the substantially vertical conductive pillar, each first memory cell comprising a respective portion of a first charge trap adjacent to the first side of the substantially vertical conductive pillar and a respective first control gate adjacent to the respective portion…

Assignees

• Micron Technology Inc

Inventors

• Pekny Theodore T

Classifications

• H10D30/693

  Electricity · mapped topic

• H10D88/00

  Electricity · mapped topic

• H10D64/037

  Electricity · mapped topic

• H10D62/115

  Electricity · mapped topic

• H01L27/11568

  Electricity · mapped topic