Through silicon via structure, method of formation, and integration in semiconductor substrate

Patent metadata

Field	Value
Publication number	US-9147609-B2
Application number	US-201213415744-A
Country	US
Kind code	B2
Filing date	Mar 8, 2012
Priority date	Oct 7, 2011
Publication date	Sep 29, 2015
Grant date	Sep 29, 2015

Abstract

Various implementations of through silicon vias with pinched off regions are disclosed. A semiconductor substrate includes a plurality of the through silicon vias disposed in the substrate and extending from a top surface of the substrate to a bottom surface of the substrate. A conductive filler is disposed within each of the plurality of through silicon vias, each of the plurality of through silicon vias having a hollow center which reduces thermal stress in the semiconductor substrate. The plurality of through silicon vias also have pinched off regions at the bottom and/or the top portions of the through silicon vias, which prevent contamination during processing of the semiconductor substrate.

First claim

The invention claimed is:

1. A semiconductor substrate having a plurality of devices, said semiconductor substrate comprising:
a plurality of through silicon vias disposed in said substrate extending from a top surface of said substrate to a bottom surface of said substrate;
a conductive filler disposed within each of said plurality of through silicon vias, each of said plurality of through silicon vias having a hollow center to reduce thermal stress in said semiconductor substr…

Assignees

• Jebory Hadi
• Howard David J
• Newport Fab Llc

Inventors

• Jebory Hadi
• Howard David J

Classifications

• H10W20/20

  Electricity · mapped topic

• H10W20/2125

  Electricity · mapped topic

• H10W20/0261

  Electricity · mapped topic

• H10W20/023 Primary

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic