Programmable delay introducing circuit in self timed memory

Patent metadata

Field	Value
Publication number	US-9147453-B2
Application number	US-201414532174-A
Country	US
Kind code	B2
Filing date	Nov 4, 2014
Priority date	Dec 30, 2005
Publication date	Sep 29, 2015
Grant date	Sep 29, 2015

Abstract

Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since idle-lying metal capacitances are utilized, the circuitry can be implemented using a minimum amount of additional hardware. Also, the delay provided by the circuitry is a function of memory cell SPICE characteristics and core parasitic capacitances.

First claim

That which is claimed:

1. A method for introducing a programmable delay in a memory device comprising a plurality of conducting layers and at least one capacitor in a path of a signal to be delayed and being formed in a portion of the plurality of conducting layers, the method comprising:
controlling the at least one capacitor being in the path of the signal to be delayed using at least one switch coupled to the at least one capacitor, with a signal introducing the programmable delay passing through the at least one switch; and
controlling a state of the at least one switch based upon a selection signal.

2. The method according to claim 1 , wherein the memory device further comprises memory cell columns and a reference column; and wherein the portion of the conducting layers defining the at least one capacitor is part of the memory cell columns.

3. The method according to claim 1 , wherein the memory device further comprises a plurality of word line drivers adjacent a reference column; and wherein the portion of the conducting layers defining the at least one capacitor is over the plurality of word line drivers.

4. The method according to claim 1 , wherein the memory device further comprises a word line driver in a word line decoder adjacent a reference column; and wherein the portion of the conducting layers defining the at least one capacitor is over the word line driver.

5. The method according to claim 1 , wherein the memory device further comprises at least one sense amplifier; and wherein the signal to be delayed comprises a RESET signal that produces a sense enable signal to enable the at least one sense amplifier.

6. The method according to claim 1 , wherein the selection signal comprises an externally generated selection signal.

7. A method for introducing a programmable delay in a memory device comprising a plurality of conducting layers and at least one capacitor formed in a portion of the plurality of conducting layers, the method comprising:
controlling the at least one capacitor being in a path of a signal to be delayed using at least one switch coupled to the at least one capacitor, the at least one switch also being in the path of the signal to be delayed, with a signal introducing the programmable delay passing through the at least one switch; and
controlling a state of the at least one switch based upon an external selection signal.

8. The method according to claim 7 , wherein the memory device further comprises memory cell columns and a reference column; and wherein the portion of the conducting layers defining the at least one capacitor is part of the memory cell columns.

9. The method according to claim 7 , wherein the memory device further comprises a plurality of word line drivers adjacent a reference column; and wherein the portion of the conducting layers defining the at least one capacitor is over the plurality of word line drivers.

10. The method according to claim 7 , wherein the memory device further comprises a word line driver in a word line decoder adjacent a reference column; and wherein the portion of the conducting layers defining the at least one capacitor is over the word line driver.

11. The method according to claim 7 , wherein the memory device further comprises at least one sense amplifier; and wherein the signal to be delayed comprises a RESET signal that produces a sense enable signal to enable the at least one sense amplifier.

12. The method according to claim 7 , wherein the selection signal comprises an externally generated selection signal.

13. A method for introducing a programmable delay in a memory device comprising a plurality of conducting layers and at least one capacitor being formed in a portion of the plurality of conducting layers, the method comprising:
controlling the at least one capacitor being in a path of a signal to be delayed using at least one switch coupled to the at least one capacitor, the at least one switch also being in the path of the signal to be delayed, with a signal introducing the programmable delay passing through the at least one switch; and
controlling a state of the at least one switch based upon a selection signal.

14. The method according to claim 13 , wherein the memory device further comprises memory cell columns and a reference column; and wherein the portion of the conducting layers defining the at least one capacitor is part of the memory cell columns.

15. The method according to claim 13 , wherein the memory device further comprises a plurality of word line drivers adjacent a reference column; and wherein the portion of the conducting layers defining the at least one capacitor is over the plurality of word line drivers.

16. The method according to claim 13 , wherein the memory device further comprises a word line driver in a word line decoder adjacent a reference column; and wherein the portion of the conducting layers defining the at least one capacitor is over the word line driver.

17. The method according to claim 13 , wherein the memory device further comprises at least one sense amplifier; and wherein the signal to be delayed comprises a RESET signal that produces a sense enable signal to enable the at least one sense amplifier.

Assignees

• St Microelectronics Int Nv

Inventors

• Kohli Nishu
• Bhargava Mudit
• Kumar Shishir

Classifications

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C7/06

  Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} · CPC title

• G11C7/08 Primary

  Control thereof · CPC title

• G11C29/50012

  of timing · CPC title

• G11C29/12015

  comprising clock generation or timing circuitry · CPC title