Programmable physical address mapping for memory

Patent metadata

Field	Value
Publication number	US-9146846-B2
Application number	US-201213617673-A
Country	US
Kind code	B2
Filing date	Sep 14, 2012
Priority date	Sep 14, 2012
Publication date	Sep 29, 2015
Grant date	Sep 29, 2015

Abstract

A memory implements a programmable physical address mapping that can change to reflect changing memory access patterns, observed or anticipated, to the memory. The memory employs address decode logic that can implement any of a variety of physical address mappings between physical addresses and corresponding memory locations. The physical address mappings may locate the data within one or more banks and rows of the memory so as to facilitate more efficient memory accesses for a given access pattern. The programmable physical address mapping employed by the hardware of the memory can include, but is not limited to, hardwired logic gates, programmable look-up tables or other mapping tables, reconfigurable logic, or combinations thereof. The physical address mapping may be programmed for the entire memory or on a per-memory region basis.

First claim

What is claimed is:

1. A memory comprising:
a set of memory cells arranged as a plurality of rows and one or more banks;
address decode logic having programmable physical address mapping, the address decode logic to select a bank and a row of the selected bank for a memory access based on the programmable physical address mapping and a physical address associated with the memory access, the address decode logic comprising:
a plurality of mapping tables, each mapping table representing a corresponding physical address mapping of a plurality of physical address mappings including the programmable physical address mapping;
a programmable storage element to store an indicator of a selected mapping table of the plurality of mapping tables; and
logic coupled to the programmable storage element and having access to the selected mapping table, the logic to perform a lookup into the selected mapping table to determine which bank is to be accessed for the memory access and to determine a bank offset identifying a row of the bank to be accessed for the memory access, wherein the logic is to perform the lookup using the physical address associated with the memory access; and

access analysis logic to determine an access pattern of memory accesses to the memory, to select a physical address mapping based on the access pattern, and to program the address decode logic to implement the selected physical address mapping, wherein the access analysis logic is to select a column-major address mapping as the physical address mapping responsive to the access pattern identifying a stride patterns greater than one and to select a row-major address mapping as the physical address mapping responsive to the access pattern identifying a stride, pattern equal to one.

2. The memory of claim 1 , wherein the programmable physical address mapping includes a space tiling physical address mapping.

3. The memory of claim 1 , wherein:
the address decode logic comprises bank decode logic for each bank, the bank decode logic to determine, based on the physical address and the programmable physical address mapping, whether the bank corresponding to the bank decode logic is to be accessed for the memory access and, responsive to determining the corresponding bank is to be accessed for the memory access, to determine a bank offset identifying a row of the bank corresponding to the bank decode logic to be accessed for the memory access.

4. The memory of claim 3 , wherein the memory further comprises:
a row buffer to buffer data at an accessed row of a corresponding bank; and
the memory is to perform the memory access using the row buffer responsive to determining the identified row is the accessed row of the corresponding bank.

5. The memory of claim 1 , wherein the mapping tables are programmable.

6. The memory of claim 1 , wherein the access analysis logic further is to select the physical address mapping based on hint information provided from a component external to the memory.

7. The memory of claim 1 , wherein, for data stored at the memory according to a previous physical address mapping, the memory is to restore the data at the memory according to the selected physical address mapping.

8. The memory of claim 1 , wherein the memory further comprises:
a row buffer to buffer data at an accessed row of an accessed bank; and
the access analysis logic is to select a physical address mapping expected to improve a frequency at which successive memory accesses map to the accessed row stored in the row buffer.

9. In a memory comprising one or more banks, a method comprising:
determining an access pattern of memory accesses to the memory;
selecting a column-major address mapping as a first physical address mapping responsive to the access pattern identifying a stride patterns greater than one and selecting a row-major address mapping as the first physical address mapping responsive to the access pattern identifying a stride pattern equal to one'
programming address decode logic of the memory to implement the first physical address mapping represented by a first mapping table selected from a plurality of mapping tables maintained at the memory, each mapping table representing a corresponding physical address mapping of a plurality of physical address mappings;
performing, using the address decode logic, a lookup into the first mapping table to select a first bank of the one or more banks and to select a first row of a plurality of rows of the first bank, wherein the lookup is performed using a first physical address associated with a first memory access; and
performing the first memory access using the first row of the first bank.

10. The method of claim 9 , wherein programming the address decode logic to implement the first physical address mapping comprises storing a value to a programmable storage element that controls which mapping table of the plurality of mapping tables is implemented by the address decode logic.

11. The method of claim 9 , wherein:
the first physical address mapping is implemented for a first memory region of a plurality of memory regions; and
performing the lookup to select the first bank and to select the first row based on the first physical address mapping is responsive to the first memory region encompassing the first physical memory address; and
wherein the method further includes:
programming the address decode logic to implement a second physical address mapping for a second memory region of the plurality of memory regions, the second physical address mapping represented by a second mapping table selected from the plurality of mapping tables;
performing, using the address decode logic, a lookup into the second mapping table to select a second bank of the one or more banks and to select a second row of a plurality of rows of the second bank based on a second physical address associated with a second memory access responsive to the second memory region encompassing the second physical memory address; and
performing the second memory access using the second row of the second bank.

12. The method of claim 9 , further comprising:
programming the address decode logic to implement a second physical address mapping represented by a second mapping table selected from the plurality of mapping tables;
performing, using the address decode logic, a lookup into the second mapping table to select a second bank of the one or more banks and to select a second row of a plurality of rows of the second bank based on a second physical address associated with a second memory access; and
performing the second memory access using the second row of the second bank.

13. The method of claim 12 , further comprising:
selecting the second physical address mapping for implementation responsive to an analysis by the memory of memory accesses performed using the first physical address mapping.

14. The method of claim 12 , further comprising:
selecting the second physical address mapping further based on hint information provided from a component external to the memory.

15. The method of claim 12 , further comprising:
transposing data stored at memory locations based on the first physical address mapping to memory locations based on the second physical address mapping responsive to programming the address decode logic to implement the second physical address mapping.

16. The method of claim 15 , wherein transposing the data comprises:
reading the data from the memory to temporary storage using the first physical address mapping; and
storing the data back to the memory from the temporary storage using the

Assignees

• Loh Gabriel H
• Breternitz Jr Mauricio
• Advanced Micro Devices Inc

Inventors

• Loh Gabriel H
• Breternitz Jr Mauricio

Classifications

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/00 Primary

  Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title

• G06F12/0207

  with multidimensional access, e.g. row/column, matrix · CPC title

• G06F12/0653

  with centralised address assignment · CPC title

• G06F12/0223 Primary

  User address space allocation, e.g. contiguous or non contiguous base addressing · CPC title