Semiconductor device and method for forming the same
US-2024395669-A1 · Nov 28, 2024 · US
Semiconductor device and method of manufacturing the same
US9136396B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9136396-B2 |
| Application number | US-201313905213-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 30, 2013 |
| Priority date | Dec 12, 2012 |
| Publication date | Sep 15, 2015 |
| Grant date | Sep 15, 2015 |
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Abstract
Official abstract text for this publication.
A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of manufacturing a semiconductor device, the method comprising: forming devices on a front surface of a substrate, each of the devices including a source electrode, a drain electrode, and a gate electrode, and the substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer which are sequentially stacked; forming a via-hole penetrating the substrate by etching a back su…
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Classifications
Electricity · mapped topic
Electricity · mapped topic
- H10W20/023Primary
Electricity · mapped topic
Electricity · mapped topic
- H10P95/00Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9136396B2 cover?
- A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and expo…
- Who is the assignee on this patent?
- Korea Electronics Telecomm
- What technology area does this patent fall under?
- Primary CPC classification H10W20/023. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).