Chip packaging method, chip packaging module, and embedded substrate chip packaging structure
US-2024413138-A1 · Dec 12, 2024 · US
Integrated chip package structure using silicon substrate and method of manufacturing the same
US9136246B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9136246-B2 |
| Application number | US-75504204-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 9, 2004 |
| Priority date | Dec 31, 2001 |
| Publication date | Sep 15, 2015 |
| Grant date | Sep 15, 2015 |
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Abstract
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An integrated chip package structure and method of manufacturing the same is by adhering dies on a silicon substrate and forming a thin-film circuit layer on top of the dies and the silicon substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.
First claim
Opening claim text (preview).
What is claimed is: 1. A chip package comprising: a substrate having a surface; a die-surrounding layer directly on said surface of said substrate; a die having a backside surface directly on said surface of said substrate, said die disposed between a first portion of said die-surrounding layer and a second portion of said die-surrounding layer, wherein said die has an active surface substantially coplanar with a first surface of said die-surrounding layer, wherein said die co…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9136246B2 cover?
- An integrated chip package structure and method of manufacturing the same is by adhering dies on a silicon substrate and forming a thin-film circuit layer on top of the dies and the silicon substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fa…
- Who is the assignee on this patent?
- Lin Mou-Shiung, Lee Jin-Yuan, Huang Ching-Cheng, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification H10W40/10. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).