Electroplated solder for high-temperature interconnect

Patent metadata

Field	Value
Publication number	US-9136237-B2
Application number	US-201314109616-A
Country	US
Kind code	B2
Filing date	Dec 17, 2013
Priority date	Dec 17, 2013
Publication date	Sep 15, 2015
Grant date	Sep 15, 2015

Abstract

This chip package includes a substrate having a multilayer electroplated stack disposed on a surface of the substrate. The multilayer electroplated stack may include one or more instances of alternating layers of gold and tin, where relative thicknesses of the alternating layers, when melted, result in a chemical composition having an initial melting temperature to form a bump and a subsequent melting temperature to reflow the bump that is higher than the initial melting temperature. For example, the chemical composition may correspond to a non-equilibrium gold-tin alloy.

First claim

What is claimed is:

1. A chip package, comprising:
a substrate having a surface; and
a multilayer electroplated stack, disposed on the surface, with one or more instances of alternating layers of gold and tin, wherein relative thicknesses of the alternating layers, when melted, result in a chemical composition having an initial melting temperature to form a bump and a subsequent melting temperature to reflow the bump that is higher than the initial melting temperature,
wherein the chip package further includes a bond pad disposed on the surface and the multilayer electroplated stack is disposed on the bond pad, and wherein the chip package further includes a multilayer stack of nickel and gold disposed between the bond pad and the multilayer electroplated stack.

2. The chip package of claim 1 , wherein the chemical composition is approximately 80% gold and 20% tin.

3. The chip package of claim 1 , wherein the chemical composition includes between approximately 16-80% gold.

4. The chip package of claim 1 , wherein a given layer in an instance of the alternating layers has a thicknesses between 0.5-5 μm.

5. The chip package of claim 1 , wherein a difference between the subsequent melting temperature and the initial melting temperature is approximately 20% of the initial melting temperature.

6. The chip package of claim 1 , wherein a number of instances of the alternating layers corresponds to a target height of the bump.

7. The chip package of claim 6 , wherein the target height is between 5-100 μm.

8. The chip package of claim 1 , wherein the chip package further includes a seed layer disposed between the multilayer stack of nickel and gold and the multilayer electroplated stack.

9. The chip package of claim 1 , wherein the chip package further includes a copper pillar disposed between the bond pad and the multilayer electroplated stack.

10. A multi-chip module (MCM), comprising:
a first substrate having a first surface, wherein a first bond pad is disposed on the first surface; and
a second substrate having a second surface, wherein a bump disposed on the second surface is coupled to the first bond pad, and
wherein the bump includes a chemical composition of gold and tin having a subsequent melting temperature to reflow the bump that is higher than an initial melting temperature of the bump,
wherein the second substrate further includes a second bond pad disposed on the second surface and the bump is disposed on the second bond pad, and wherein the second substrate further includes a multilayer stack of nickel and gold disposed between the second bond pad and the bump.

11. The MCM of claim 10 , wherein the chemical composition corresponds to a non-equilibrium gold-tin alloy.

12. The MCM of claim 10 , wherein the chemical composition is approximately 80% gold and 20% tin.

13. The MCM of claim 10 , wherein the chemical composition includes between approximately 16-80% gold.

14. The MCM of claim 10 , wherein a difference between the subsequent melting temperature and the initial melting temperature is approximately 20% of the initial melting temperature.

15. The MCM of claim 10 , wherein the second substrate further includes a copper pillar disposed between the second bond pad and the bump.

16. A method for fabricating a bump, the method comprising:
disposing a multilayer electroplated stack on a surface of a substrate, wherein the multilayer electroplated stack includes one or more instances of alternating layers of gold and tin, and wherein relative thicknesses of the alternating layers, when melted, result in a chemical composition having an initial melting temperature; and
melting the multilayer electroplated stack at a temperature of at least the initial melting temperature to form the bump, wherein a subsequent melting temperature to reflow the bump is higher than the initial melting temperature.

17. The method of claim 16 , wherein the chemical composition is approximately 80% gold and 20% tin.

18. The method of claim 16 , wherein the chemical composition includes between approximately 16-80% gold.

19. The method of claim 16 , wherein a given layer in an instance of the alternating layers has a thickness between 0.5-5 μm.

20. The method of claim 16 , wherein a difference between the subsequent melting temperature and the initial melting temperature is approximately 20% of the initial melting temperature.

Assignees

• Oracle Int Corp

Inventors

• Thacker Hiren D
• Cunningham John E

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/07255

  changes in materials · CPC title

• H10W72/07236

  Soldering or alloying · CPC title