Semiconductor manufacturing process system and method

Patent metadata

Field	Value
Publication number	US-9136190-B2
Application number	US-201313795760-A
Country	US
Kind code	B2
Filing date	Mar 12, 2013
Priority date	Aug 29, 2012
Publication date	Sep 15, 2015
Grant date	Sep 15, 2015

Abstract

According to one embodiment, a wafer processing device includes a processed number counting unit that counts a number of processed wafers, and a maintenance post-processing unit that executes a dummy lot process and a QC lot process after a maintenance process. A wafer preparation device prepares the dummy lot and the QC lot, when a first processed number is counted by the processed number counting unit. When a second processed number is counted by the processed number counting unit, a carrier device carries the dummy lot and the QC lot to the wafer processing device simultaneous with the maintenance process, before the maintenance process is completed.

First claim

What is claimed is:

1. A semiconductor manufacturing process system comprising:
a storage container configured to store wafers in a predetermined number;
a wafer processing device configured to eject a wafer from the storage container placed on a port, and perform a predetermined process to the wafer;
a QC information measuring device configured to measure QC information that is a parameter indicating a process quality in the wafer processing device;
a wafer preparation devi…

Assignees

• Toshiba Kk

Inventors

• Okada Eiichi

Classifications

• H10P74/23 Primary

  Electricity · mapped topic

• B24B37/042 Primary

  Operations & Transport · mapped topic

• G05B2219/45031

  Physics · mapped topic

• G05B19/41865

  Physics · mapped topic

• G05B2219/32269

  Physics · mapped topic