Semiconductor device and method for forming the same
US-2024395669-A1 · Nov 28, 2024 · US
Through silicon via (TSV) structure and process thereof
US9136170B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9136170-B2 |
| Application number | US-201213483074-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 30, 2012 |
| Priority date | May 30, 2012 |
| Publication date | Sep 15, 2015 |
| Grant date | Sep 15, 2015 |
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- Title
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Abstract
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A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.
First claim
Opening claim text (preview).
What is claimed is: 1. A through silicon via structure located in a recess of a substrate, comprising: a barrier layer covering the surface of the recess; a buffer layer having a top surface with different smoothness from a bottom surface covering the barrier layer; and a conductive layer located on the buffer layer and filling the recess, thereby constituting a through silicon via structure, wherein the contact surface between the conductive layer and the buffer layer is smoo…
Assignees
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Classifications
- H10W20/023Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10W20/036Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9136170B2 cover?
- A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and…
- Who is the assignee on this patent?
- Chen jia-jia, Hsu Chi-Mao, Cheng Tsun-Min, and 6 more
- What technology area does this patent fall under?
- Primary CPC classification H10W20/023. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).