Embedded nonvolatile memory elements having resistive switching characteristics

Patent metadata

Field	Value
Publication number	US-9129894-B2
Application number	US-201213621371-A
Country	US
Kind code	B2
Filing date	Sep 17, 2012
Priority date	Sep 17, 2012
Publication date	Sep 8, 2015
Grant date	Sep 8, 2015

Abstract

Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line.

First claim

What is claimed:

1. A nonvolatile memory assembly comprising:
a set of signal lines comprising a bit line, a word line, and a source line;
a nonvolatile memory element comprising
a first layer operable as a first electrode connected to the bit line and comprising titanium nitride,
a second layer operable as a second electrode and comprising polysilicon, and
a third layer comprising hafnium oxide having oxygen vacancies, wherein the third layer is provided between the first layer and the second layer; and

a transistor comprising a source electrically connected to the source line, a gate electrically connected to the word line, and a drain electrically connected to the second layer of the nonvolatile memory element; and
wherein the bit line, the word line, and the source line are located within a first interlayer dielectric (ILD) layer,
wherein the nonvolatile memory element is located within a second ILD layer disposed under the first ILD layer, such that the bit line, the word line, and the source line are all disposed on one side of the nonvolatile memory element, and
wherein the transistor is located within a third ILD layer disposed under the second ILD layer.

2. The nonvolatile memory assembly of claim 1 , wherein the hafnium oxide of the third layer of the nonvolatile memory element has a stoichiometric formula of HfO x with X being between 1.7 and 1.9.

3. The nonvolatile memory assembly of claim 1 , wherein the third layer of the nonvolatile memory element has a thickness of between 15 Angstroms and 100 Angstroms.

4. The nonvolatile memory assembly of claim 1 , wherein the polysilicon of the second layer of the nonvolatile memory element comprises an n-dopant.

5. The nonvolatile memory assembly of claim 1 , wherein the polysilicon of the second layer of the nonvolatile memory element comprises a dopant present at a concentration of between 1,019 and 1,020 atoms per centimeter cubed.

6. The nonvolatile memory assembly of claim 1 , wherein the second layer of the nonvolatile memory element further comprises a sublayer at an interface with the third layer, the sublayer comprising silicon oxide.

7. The nonvolatile memory assembly of claim 1 , wherein the second layer of the nonvolatile memory element has a thickness of between 100 Angstroms and 1,000 Angstroms.

8. The nonvolatile memory assembly of claim 1 , wherein the first layer of the nonvolatile memory element has a thickness of between 200 Angstroms and 2,000 Angstroms.

9. The nonvolatile memory assembly of claim 1 , wherein the first layer of the nonvolatile memory element is connected to the bit line using a contact comprising tungsten.

10. The nonvolatile memory assembly of claim 9 , wherein the nonvolatile memory element further comprises a fourth layer operable as a diffusion barrier layer, the fourth layer being located between the first layer of the nonvolatile memory element and the contact.

11. The nonvolatile memory assembly of claim 10 , wherein the fourth layer has a thickness of between 300 Angstroms and 800 Angstroms.

12. The nonvolatile memory assembly of claim 1 , wherein a resistance between the source and the drain is controllable between about 1 kOhm and 1 MOhm by applying a potential to the word line.

13. The nonvolatile memory assembly of claim 1 , wherein the hafnium oxide is configured to change its resistivity state when a voltage of less than 3.0V is applied to the third layer of the nonvolatile memory element.

14. The nonvolatile memory assembly of claim 1 , wherein the nonvolatile memory element has a thickness of between 1,000 Angstroms and 5,000 Angstroms.

15. A nonvolatile memory assembly comprising:
a set of signal lines comprising a bit line, a first word line, a second word line, a first source line, and a second source line;
a nonvolatile memory element comprising a first layer operable as a first electrode connected to the bit line and comprising titanium nitride, a second layer operable as a second electrode and comprising polysilicon, and a third layer comprising hafnium oxide having oxygen vacancies, wherein the third layer is provided between the first layer and the second layer;
a first transistor comprising a first source electrically connected to the first source line, a first gate electrically connected to the first word line, and a first drain electrically connected to the second layer of the nonvolatile memory element; and
a second transistor comprising a second source electrically connected to the second source line, a second gate electrically connected to the second word line, and a second drain electrically connected to the second layer of the nonvolatile memory element
wherein the bit line, the first word line, the second word line, the first source line, and the second source line are located within a first interlayer dielectric (ILD) layer,
wherein the nonvolatile memory element is located within a second ILD layer disposed under the first ILD layer, such that the bit line, the first word line, the second word line, the first source line, and the second source line are all disposed on one side of the nonvolatile memory element, and
wherein the first transistor and the second transistor are located within a third ILD layer disposed under the second ILD layer.

16. The nonvolatile memory assembly of claim 15 , wherein the first source line and the second source line are the same component of the nonvolatile memory assembly.

17. A method of operating a nonvolatile memory assembly, the method comprising:
providing the nonvolatile memory assembly comprising (i) a set of signal lines comprising a bit line, a word line, and a source line, (ii) a nonvolatile memory element comprising a first electrode connected to the bit line and comprising titanium nitride, a second electrode comprising polysilicon, and a resistive switching layer provided between the first and second electrodes and comprising hafnium oxide having oxygen vacancies, and (iii) a transistor comprising a source electrically connected to the source line, a gate electrically connected to the word line, and a drain electrically connected to the second electrode,
wherein the bit line, the word line, and the source line are located within a first interlayer dielectric (ILD) layer,
wherein the nonvolatile memory element is located within a second ILD layer disposed under the first ILD layer, such that the bit line, the word line, and the source line are all disposed on one side of the nonvolatile memory element, and
wherein the transistor is located within a third ILD layer disposed under the second ILD layer;

applying a first potential to the word line resulting in a first electrical resistance between the drain and the source being at a first level; and
maintaining the source line at a ground potential while applying a second potential to the bit line resulting in a first current of less than 100 microamperes flowing through the resistive switching layer and changing a resistive state of the hafnium oxide.

18. The method of claim 17 , wherein the second potential is less than about 3.0 Volts.

19. The method of claim 17 , further comprising:
applying a third potential to the word line resulting in a second electrical resistance between the drain and the source being at a second level that is smaller than the first level; and
maintaining the source line at the ground potential while applying a fourth potential to the bit line resulting in a second current flowing through the resistive switching layer, the second current being smaller than the first current

Assignees

• Hashim Imran
• Chiang Tony
• Gopal Vidyut
• Wang Yun
• Intermolecular Inc

Inventors

• Hashim Imran
• Chiang Tony
• Gopal Vidyut
• Wang Yun

Classifications

• G11C2213/74

  Array wherein each memory cell has more than one access device · CPC title

• G11C13/0007 Primary

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C2213/32

  Material having simple binary metal oxide structure · CPC title