Semiconductor devices and methods of manufacturing
US-12166025-B2 · Dec 10, 2024 · US
Bonded structures for package and substrate
US9123788B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9123788-B2 |
| Application number | US-201414480439-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 8, 2014 |
| Priority date | Aug 17, 2012 |
| Publication date | Sep 1, 2015 |
| Grant date | Sep 1, 2015 |
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Abstract
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The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.
First claim
Opening claim text (preview).
What is claimed is: 1. A method, comprising: aligning a first conductive post on a die package with a solder layer, the solder layer being in physical contact with a metal pad over a substrate; and bonding the first conductive post to the solder layer, wherein after bonding a surface of the first conductive post facing a center of the die package is not wetted by the solder layer, and wherein a surface of the first conductive post not facing the center of the die package is wett…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9123788B2 cover?
- The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification H10W72/012. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).