MOS semiconductor device

Patent metadata

Field	Value
Publication number	US-9123767-B2
Application number	US-201414219709-A
Country	US
Kind code	B2
Filing date	Mar 19, 2014
Priority date	Mar 21, 2013
Publication date	Sep 1, 2015
Grant date	Sep 1, 2015

Abstract

An MOS semiconductor device including an MOS gate structure is disclosed. The MOS semiconductor device includes a p-type well region selectively disposed on the surface layer of an n-type drift layer formed on a semiconductor substrate forming an n-type drain region; an n-type source region selectively disposed on the surface layer of the p-type well region; and a gate electrode placed, via an insulating film, on the surface of a channel formation region on the surface layer of the p-type well region sandwiched between the n-type source region and the surface layer of the n-type drain region, wherein a surface in the channel formation region has a level difference formed in the direction of the peripheral length, and all over the length, of the channel formation region.

First claim

What is claimed is:

1. A MOS semiconductor device including a MOS gate structure, the MOS semiconductor device comprising:
a first conductivity type drain region;
a drift region of the first conductivity type that is formed on the drain region;
a second conductivity type well region selectively disposed on a surface of the first conductivity type drift region;
a source region of the first conductivity type selectively disposed on a surface of the second conductivity type wel…

Assignees

• Fuji Electric Co Ltd

Inventors

• Inoue Masanori

Classifications

• H10W90/756

  Electricity · mapped topic

• H10D62/393

  Electricity · mapped topic

• H10D62/127

  Electricity · mapped topic

• H10D12/441

  Electricity · mapped topic

• H10D64/513

  Electricity · mapped topic