FinFETs and methods for forming the same

Patent metadata

Field	Value
Publication number	US-9123743-B2
Application number	US-201313790742-A
Country	US
Kind code	B2
Filing date	Mar 8, 2013
Priority date	Mar 8, 2013
Publication date	Sep 1, 2015
Grant date	Sep 1, 2015

Abstract

Methods for forming a semiconductor device and a FinFET device are disclosed. A method comprises forming a dummy gate electrode layer over a substrate, the dummy gate electrode layer having a first height, forming a first etch stop layer on the dummy gate electrode layer, forming a first hard mask layer on the first etch stop layer, and patterning the first hard mask layer. The method further comprises patterning the first etch stop layer to align with the patterned first hard mask layer, and patterning the gate electrode layer to form a dummy gate electrode, the dummy gate electrode aligning with the patterned first etch stop layer, wherein after the patterning the gate electrode layer the first hard mask layer has a vertical sidewall of a second height, the second height being less than the first height, and the first hard mask layer having a rounded top surface.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a dummy gate electrode layer over a substrate, the dummy gate electrode layer having a first height;
forming a first etch stop layer on the dummy gate electrode layer;
forming a first hard mask layer on the first etch stop layer;
patterning the first hard mask layer;
patterning the first etch stop layer to align with the patterned first hard mask layer; and
patterning the du…

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Lin yu-chao
• Hsieh Tzu-Yen
• Tai Ming-Chia
• Chen Chao-Cheng

Classifications

• H10P95/06

  Electricity · mapped topic

• H10P50/287

  Electricity · mapped topic

• H10P50/267

  Electricity · mapped topic

• H10P50/73

  Electricity · mapped topic

• H10P50/71

  Electricity · mapped topic