Chip packaging method, chip packaging module, and embedded substrate chip packaging structure
US-2024413138-A1 · Dec 12, 2024 · US
Integrated circuit packaging system with package underfill and method of manufacture thereof
US9123733B1 · US · B1
| Field | Value |
|---|---|
| Publication number | US-9123733-B1 |
| Application number | US-201313844160-A |
| Country | US |
| Kind code | B1 |
| Filing date | Mar 15, 2013 |
| Priority date | Mar 25, 2009 |
| Publication date | Sep 1, 2015 |
| Grant date | Sep 1, 2015 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
A method of manufacture of an integrated circuit packaging system includes: providing a sacrificial carrier assembly having a stack interconnector thereover; mounting an integrated circuit having a connector over the sacrificial carrier assembly with the connector over the stack interconnector; dispensing an underfill material between the sacrificial carrier assembly and the integrated circuit with the underfill material substantially free of a void; encapsulating the integrated circuit over the sacrificial carrier assembly and the underfill material; exposing the stack interconnector by removing the sacrificial carrier assembly; and forming a base array over the underfill material and the stack interconnector.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of manufacturing an integrated circuit packaging system comprising: providing a sacrificial carrier assembly having a stack interconnector thereover; mounting an integrated circuit having a connector over the sacrificial carrier assembly with the connector over the stack interconnector; dispensing an underfill material between the sacrificial carrier assembly and the integrated circuit with the underfill material substantially free of a void, th…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9123733B1 cover?
- A method of manufacture of an integrated circuit packaging system includes: providing a sacrificial carrier assembly having a stack interconnector thereover; mounting an integrated circuit having a connector over the sacrificial carrier assembly with the connector over the stack interconnector; dispensing an underfill material between the sacrificial carrier assembly and the integrated circuit …
- Who is the assignee on this patent?
- Huang Rui, Kuan Heap Hoe, Lin Yaojian, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification H10W74/012. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).