Non-hierarchical metal layers for integrated circuits

Patent metadata

Field	Value
Publication number	US-9117882-B2
Application number	US-201113158175-A
Country	US
Kind code	B2
Filing date	Jun 10, 2011
Priority date	Jun 10, 2011
Publication date	Aug 25, 2015
Grant date	Aug 25, 2015

Abstract

An integrated circuit structure includes a semiconductor substrate, and a first metal layer over the semiconductor substrate. The first metal layer has a first minimum pitch. A second metal layer is over the first metal layer. The second metal layer has a second minimum pitch smaller than the first minimum pitch.

First claim

What is claimed is:

1. An integrated circuit structure comprising:
a semiconductor substrate;
a first metal layer over the semiconductor substrate, wherein the first metal layer comprises first metal lines therein, and wherein the first metal layer has a first minimum pitch, with the first minimum pitch measured in a first horizontal direction perpendicular to lengthwise directions of first two metal lines that have the first minimum pitch;
a second metal layer over the first metal layer, wherein the second metal layer comprises second metal lines therein, and wherein the second metal layer has a second minimum pitch smaller than the first minimum pitch, with the second minimum pitch measured in a second horizontal direction perpendicular to lengthwise directions of second two metal lines that have the second minimum pitch; and
metal vias between the first metal layer and the second metal layer.

2. The integrated circuit structure of claim 1 further comprising:
a third metal layer under the first metal layer; and
gate electrodes over the semiconductor substrate and under the third metal layer, wherein at least some of gate electrodes form parts of transistors, and wherein the third metal layer has a third minimum pitch smaller than the first minimum pitch, and smaller than a fourth minimum pitch of the gate electrodes, with the third minimum pitch measured in a third horizontal direction perpendicular to lengthwise directions of third two metal lines that have the third minimum pitch, and the fourth minimum pitch measured in a fourth horizontal direction perpendicular to lengthwise directions of two gate electrodes that have the fourth minimum pitch.

3. The integrated circuit structure of claim 2 , wherein the first minimum pitch is substantially equal to the fourth minimum pitch.

4. The integrated circuit structure of claim 1 , wherein a first thickness of the first metal layer is greater than a second thickness of the second metal layer.

5. The integrated circuit structure of claim 4 , wherein the first thickness is between about 120 percent and about 150 percent the second thickness.

6. The integrated circuit structure of claim 1 , wherein the first and the second metal layers comprise metal lines comprising copper, and wherein the metal lines in the first and the second metal layers and respective underlying vias have dual-damascene structures.

7. The integrated circuit structure of claim 1 , wherein the first minimum pitch is between about 80 nm and about 100 nm, and the second minimum pitch is between about 40 nm and about 80 nm.

8. The integrated circuit structure of claim 1 further comprising:
a diffusion barrier layer comprising:
bottom portions underlying and in physical contact with bottom surfaces of the metal vias, wherein the bottom portions have top surfaces contacting bottom surfaces of the metal vias, and bottom surfaces contacting top surface of the first metal lines; and
sidewall portions contacting sidewalls of the metal vias.

9. The integrated circuit structure of claim 1 , wherein the first minimum pitch is the smallest pitch of all metal lines in the first metal layer, and the second minimum pitch is the smallest pitch of all metal lines in the second metal layer.

10. The integrated circuit structure of claim 2 , wherein the third metal layer is immediately over the gate electrodes, with no additional metal layer disposed between the gate electrodes and the third metal layer, and wherein the first metal layer is immediately over the third metal layer, with no additional metal layer disposed between the first metal layer and the third metal layer.

11. An integrated circuit structure comprising:
a semiconductor substrate;
a first metal layer over the semiconductor substrate, wherein the first metal layer comprises first metal lines therein, wherein the first metal layer has a first minimum pitch, and wherein the first metal layer has a first thickness;
a second metal layer over the first metal layer, wherein the second metal layer comprises second metal lines therein, and wherein the second metal layer has a second thickness smaller than the first thickness, and the second metal layer has a second minimum pitch smaller than the first minimum pitch;
a third metal layer under the first metal layer;
gate electrodes over the semiconductor substrate and under the third metal layer, wherein at least some of the gate electrodes form parts of transistors, and wherein the third metal layer has a third thickness smaller than the first thickness; and
metal vias between the first metal layer and the second metal layer.

12. The integrated circuit structure of claim 11 , wherein the first minimum pitch is substantially equal to a fourth minimum pitch of the gate electrodes.

13. The integrated circuit structure of claim 11 , wherein the first thickness is between about 120 percent and about 150 percent the second thickness.

14. The integrated circuit structure of claim 11 , wherein the first and the second metal layers comprise metal lines comprising copper, and wherein the metal lines in the first and the second metal layers and respective underlying vias have dual-damascene structures.

15. The integrated circuit structure of claim 11 , wherein the first thickness is between about 800 Å and about 1,200 Å, and the second thickness is between about 550 Å and about 750 Å.

16. The integrated circuit structure of claim 11 further comprising:
a diffusion barrier layer comprising:
bottom portions underlying and in physical contact with bottom surfaces of the metal vias, wherein the bottom portions have top surfaces contacting bottom surfaces of the metal vias, and bottom surfaces contacting top surface of the first metal lines; and
sidewall portions contacting sidewalls of the metal vias.

17. The integrated circuit structure of claim 11 , wherein the first minimum pitch is the smallest pitch of all metal lines in the first metal layer, and the second minimum pitch is the smallest pitch of all metal lines in the second metal layer.

18. An integrated circuit structure comprising:
a semiconductor substrate;
a first metal layer over the semiconductor substrate, wherein the first metal layer comprises first metal lines therein, and wherein the first metal layer has a first minimum pitch;
a second metal layer over the first metal layer, wherein the second metal layer comprises second metal lines therein, and wherein the second metal layer has a second minimum pitch smaller than the first minimum pitch;
a third metal layer under the first metal layer, wherein the third metal layer has a third minimum pitch smaller than the first minimum pitch;
gate electrodes over the semiconductor substrate and under the third metal layer, wherein at least some of the gate electrodes form parts of transistors, wherein the gate electrodes have a fourth minimum pitch greater than the third minimum pitch, and wherein the fourth minimum pitch is substantially equal to the fourth minimum pitch; and
metal vias between the first metal layer and the second metal layer.

19. The integrated circuit structure of claim 18 , wherein a first thickness of the first metal layer is greater than a second thickness of the second metal layer.

20. The integrated circuit structure of claim 18 , wherein the first and the second metal layers comprise metal lines comprising copper, and wherein the metal lines in the first and the second metal layers and respective underlying vias have dual-damascene structures.

Assignees

• Lu Lee-Chung
• Hou Yuan-Te
• Lin Shyue-Shyh
• Tien Li-Chun
• Chen Dian-Hau
• Taiwan Semiconductor Mfg

Inventors

• Lu Lee-Chung
• Hou Yuan-Te
• Lin Shyue-Shyh
• Tien Li-Chun
• Chen Dian-Hau

Classifications

• H10P50/73 Primary

  using masks for insulating materials · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title