Device with engineered epitaxial region and methods of making same

Patent metadata

Field	Value
Publication number	US-9117843-B2
Application number	US-201113232738-A
Country	US
Kind code	B2
Filing date	Sep 14, 2011
Priority date	Sep 14, 2011
Publication date	Aug 25, 2015
Grant date	Aug 25, 2015

Abstract

An engineered epitaxial region compensates for short channel effects of a MOS device by providing a blocking layer to reduce or prevent dopant diffusion while at the same time reducing or eliminating the side effects of the blocking layer such as increased leakage current of a BJT device and/or decreased breakdown voltage of a rectifier. These side effects are reduced or eliminated by a non-conformal dopant-rich layer between the blocking layer and the substrate, which lessens the abruptness of the junction, thus lower the electric field at the junction region. Such a scheme is particularly advantageous for system on chip applications where it is desirable to manufacture MOS, BJT, and rectifier devices simultaneously with common process steps.

First claim

What is claimed is:

1. A method for forming a device comprising:
forming in a substrate a recess having a bottom and sidewalls;
forming an epitaxial layer over the bottom of the recess;
forming an epitaxial blocking layer over the epitaxial layer and over the sidewalls of the recess, the epitaxial blocking layer having a different lattice constant than the epitaxial layer; and
substantially filling the recess with an epitaxially grown material.

2. The method of claim 1 wherein the step of forming an epitaxial layer on the bottom of the recess includes:
epitaxially growing the epitaxial layer on the bottom and on the sidewalls of the recess; and
selectively or isotropically removing the epitaxial layer from the sidewalls of the recess.

3. The method of claim 2 wherein selectively removing the epitaxial layer from the sidewalls of the recess includes:
etching using an etchant gas selected from the group consisting essentially of GeH4, Cl2 and combinations thereof.

4. The method of claim 1 wherein the step of forming an epitaxial layer on the bottom of the recess includes forming an in-situ doped silicon layer using metal oxide chemical vapor deposition (MOCVD).

5. The method of claim 1 wherein the step of forming an epitaxial blocking layer includes forming an in-situ carbon doped silicon layer using MOCVD.

6. The method of claim 1 wherein the step of substantially filling the recess with an epitaxially grown material includes forming an in-situ doped silicon layer using a same dopant as used for the epitaxial layer.

7. The method of claim 1 wherein the epitaxial layer, the epitaxial blocking layer, and the epitaxially grown material are formed in a same chamber.

8. The method of claim 1 wherein the step of forming an epitaxial layer on the bottom of the recess includes in situ doping the epitaxial layer with an impurity selected from the group consisting essentially of phosphorous, antimony, arsenic, and combinations thereof.

9. The method of claim 1 wherein the step of forming an epitaxial blocking layer includes in situ doping the blocking layer with carbon.

10. A device comprising:
a gate structure formed on a substrate;
an epitaxial source/drain region formed in the substrate, aligned to the gate structure, and having a bottom surface and a side surface;
an epitaxial layer interjacent the bottom surface of the epitaxial source/drain region and the substrate; and
an epitaxial blocking layer interjacent the bottom surface of the epitaxial source/drain region and the epitaxial layer and further interjacent the side surface of the epitaxial source/drain region and the substrate, the epitaxial blocking layer separating the epitaxial layer from the bottom surface of the epitaxial source/drain region and acting as a barrier to diffusion of dopants from the epitaxial source/drain region.

11. The device of claim 10 wherein the epitaxial source/drain region and the epitaxial layer both comprise phosphorous doped silicon.

12. The device of claim 10 wherein the epitaxial blocking layer comprises carbon doped silicon.

13. The device of claim 10 wherein the blocking layer has a thickness of about 70 Å where the blocking layer is interjacent the bottom surface of the epitaxial source/drain region and the epitaxial layer and has a thickness of about 30 Å where the blocking layer is interjacent the side surface of the epitaxial source/drain region and the substrate.

14. The device of claim 10 further comprising a gradient implant region underlying the epitaxial source/drain region and the epitaxial layer.

15. The device of claim 10 further comprising:
an epitaxial emitter region formed in the substrate and having a bottom surface and a side surface;
a second epitaxial layer interjacent the bottom surface of the epitaxial emitter region and the substrate; and
a second epitaxial blocking layer interjacent the bottom surface of the epitaxial emitter region and the epitaxial layer and further interjacent the side surface of the epitaxial emitter region and the substrate.

16. A method of forming a device comprising:
etching a semiconductor substrate to form at least one recess having a bottom and a sidewall;
epitaxially growing an in situ doped first layer, doped with a first impurity, over the bottom and the sidewall of the at least one recess;
removing the in situ doped first layer from the sidewall of the at least one recess, leaving a remaining portion of the first layer over the bottom of the at least one recess;
epitaxially growing an in situ doped second layer, doped with a second impurity, over the remaining portion of the first layer and over the sidewall of the at least one recess, wherein the second impurity is different than the first impurity; and
epitaxially growing an in situ doped material, doped with the first impurity, to fill the at least one recess.

17. The method of claim 16 wherein the first impurity is selected from the group consisting of phosphorous, arsenic, and antimony and the second impurity is selected from the group consisting of carbon, germanium, and xenon.

18. The method of claim 17 wherein the at least one recess includes a first recess and a second recess and further comprising forming a metal oxide semiconductor (MOS) transistor using the first recess and forming a bipolar junction transistor (BJT) using the second recess.

19. The method of claim 16 wherein the step of removing the in situ doped first layer from the sidewall of the at least one recess includes an isotropic etch process.

20. The method of claim 16 further comprising:
etching the semiconductor substrate to form a second recess simultaneously with forming the at least one recess;
epitaxially growing the in situ doped first layer on a bottom and a sidewall of the second recess;
selectively removing the in situ doped first layer from the sidewall of the second recess, leaving a remaining portion of the in situ doped first layer on the bottom of the second recess;
epitaxially growing the in situ doped second layer on the remaining portion of the first layer and on the sidewall of the second recess; and
epitaxially growing an in situ doped material to fill the second recess.

Assignees

• Wong King-Yuen
• Lu Chia-Yu
• Su Chien-Chang
• Lin Yen-Chun
• Pai Yi-Fang
• Lin Da-Wen
• Taiwan Semiconductor Mfg

Inventors

• Wong King-Yuen
• Lu Chia-Yu
• Su Chien-Chang
• Lin Yen-Chun
• Pai Yi-Fang
• Lin Da-Wen

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10D84/401

  Combinations of FETs or IGBTs with BJTs · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/0109

  the at least one component covered by H10D12/00 or H10D30/00 being a MOS device · CPC title