Semiconductor devices and methods of manufacturing
US-12166025-B2 · Dec 10, 2024 · US
Bump structure and method of forming same
US9111817B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9111817-B2 |
| Application number | US-201213712722-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 12, 2012 |
| Priority date | Sep 18, 2012 |
| Publication date | Aug 18, 2015 |
| Grant date | Aug 18, 2015 |
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Abstract
Official abstract text for this publication.
An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.
First claim
Opening claim text (preview).
What is claimed is: 1. A bump on trace (BOT) structure, comprising: a contact element supported by an integrated circuit; an under bump metallurgy (UBM) feature electrically coupled to the contact element; a metal bump on the under bump metallurgy feature; and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint, an additional metal, and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic com…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9111817B2 cover?
- An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first …
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification H10W70/093. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 18 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).