Hybrid timing recovery for burst mode receiver in passive optical networks

US9106400B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9106400-B2
Application numberUS-201213658341-A
CountryUS
Kind codeB2
Filing dateOct 23, 2012
Priority dateOct 23, 2012
Publication dateAug 11, 2015
Grant dateAug 11, 2015

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Abstract

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An apparatus for coarse phase alignment of an analog signal comprising: a tapped delay line, a coarse phase alignment logic circuit coupled to the tapped delay line, and a selector coupled to the tapped delay and the coarse phase alignment logic circuit. An apparatus for timing and data recovery for burst mode receivers comprising: a receiver, a coarse phase alignment circuit coupled to the receiver, at least one analog to digital converter (ADC) coupled to the coarse phase alignment circuit such that the coarse phase alignment circuit is positioned between the receiver and the ADC, and a fine phase alignment circuit coupled to the ADC such that the ADC is positioned between the coarse phase alignment circuit and the fine phase alignment circuit, wherein the fine phase alignment circuit produces a recovered data output.

First claim

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What is claimed is: 1. An apparatus for coarse phase alignment of an analog signal comprising: a tapped delay line configured to output N delayed signals, wherein each delayed signal has a delay based on a bit period, N, and M; a coarse phase alignment logic circuit coupled to the tapped delay line; and a selector coupled to the tapped delay line and the coarse phase alignment logic circuit and configured to receive the N delayed signals, wherein N is an integer greater than 1…

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What does patent US9106400B2 cover?
An apparatus for coarse phase alignment of an analog signal comprising: a tapped delay line, a coarse phase alignment logic circuit coupled to the tapped delay line, and a selector coupled to the tapped delay and the coarse phase alignment logic circuit. An apparatus for timing and data recovery for burst mode receivers comprising: a receiver, a coarse phase alignment circuit coupled to the rec…
Who is the assignee on this patent?
Futurewei Technologies Inc
What technology area does this patent fall under?
Primary CPC classification H04L7/0335. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).