Clock and data recovery architecture with adaptive digital phase skew
US-2015016497-A1 · Jan 15, 2015 · US
US9596108B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9596108-B2 |
| Application number | US-201414292743-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 30, 2014 |
| Priority date | May 30, 2014 |
| Publication date | Mar 14, 2017 |
| Grant date | Mar 14, 2017 |
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Described is an apparatus which comprises: a Decision Feedback Equalizer (DFE); and a phase detector, operationally coupled to the DFE, to set a sampling phase based on a first post-cursor value of a composite pulse response being substantially equal to zero when the phase detector collects data bits having current bit and next bit such that value of the current bit is unequal to a value of the next bit.
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We claim: 1. An apparatus comprising: a decision feedback equalizer; a first phase detector, operationally coupled to the decision feedback equalizer, to set a sampling phase based on a first post-cursor value of a composite pulse response being substantially equal to zero when the first phase detector collects data bits having a current bit and a next bit such that a value of the current bit is unequal to a value of the next bit; and a second phase detector to set initial con…
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