Fine-grain dynamically reconfigurable fpga architecture
US-2015381182-A1 · Dec 31, 2015 · US
Width scalable connector for high bandwidth IO interfaces
US9106217B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9106217-B2 |
| Application number | US-201113977050-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 6, 2011 |
| Priority date | Dec 6, 2011 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
Disclosed is a scalable input/output interface that has multiple bays and includes a housing surrounding a plurality of pairs of substrates. A first substrate of the pair of substrates may have a first contact surface and a second substrate of the pair of substrates may have a second contact surface that opposes the first contact surface, wherein each substrate has a connection edge. At least one integrated buffer can be coupled to either the first side or the second side of each substrate. A plurality of rows of contacts can be coupled to the opposing surfaces of each substrate of the pair of substrates, wherein each row of contacts can be stacked substantially parallel to the connection edge. Each connection edge can also be coupled to a separate integrated buffer.
First claim
Opening claim text (preview).
We claim: 1. A male input/output (IO) interface comprising: a plurality of substrates, each substrate having a connection edge with a first side and a second side; at least one integrated butler coupled to at least one of the first side and the second side of each substrate; and a plurality of rows of contacts coupled to the first side of each substrate, wherein each row of contacts is stacked substantially parallel to the connection edge. 2. The IO inter…
Assignees
Inventors
Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H03K19/0008Primary
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9106217B2 cover?
- Disclosed is a scalable input/output interface that has multiple bays and includes a housing surrounding a plurality of pairs of substrates. A first substrate of the pair of substrates may have a first contact surface and a second substrate of the pair of substrates may have a second contact surface that opposes the first contact surface, wherein each substrate has a connection edge. At least o…
- Who is the assignee on this patent?
- Jaussi James E, Pederson Bruce E, Heck Howard L, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification H03K19/0008. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).