Semiconductor device and method of manufacturing semiconductor device

US9105743B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9105743-B2
Application numberUS-201414265860-A
CountryUS
Kind codeB2
Filing dateApr 30, 2014
Priority dateSep 30, 2010
Publication dateAug 11, 2015
Grant dateAug 11, 2015

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

The semiconductor device includes a first transistor including a first impurity layer containing boron or phosphorus, a first epitaxial layer formed above the first impurity layer, a first gate electrode formed above the first epitaxial layer with a first gate insulating film formed therebetween and first source/drain regions, and a second transistor including a second impurity layer containing boron and carbon, or arsenic or antimony, a second epitaxial layer formed above the second impurity layer, a second gate electrode formed above the second epitaxial layer with a second gate insulating film thinner than the first gate insulating film formed therebetween, and second source/drain regions.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of manufacturing a semiconductor device comprising: forming a first impurity layer in a first region of a semiconductor substrate by implanting a first impurity of a first conductivity type in the first region; forming a second impurity layer in a second region of the semiconductor substrate by implanting a second impurity of the first conductivity type in the second region, a diffusion constant of the second impurity being smaller than a diffusio…

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What does patent US9105743B2 cover?
The semiconductor device includes a first transistor including a first impurity layer containing boron or phosphorus, a first epitaxial layer formed above the first impurity layer, a first gate electrode formed above the first epitaxial layer with a first gate insulating film formed therebetween and first source/drain regions, and a second transistor including a second impurity layer containing…
Who is the assignee on this patent?
Fujitsu Semiconductor Ltd
What technology area does this patent fall under?
Primary CPC classification H10W10/031. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).