Wafer dicing method for improving die packaging quality

Patent metadata

Field	Value
Publication number	US-9105710-B2
Application number	US-201314091014-A
Country	US
Kind code	B2
Filing date	Nov 26, 2013
Priority date	Aug 30, 2013
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

In embodiments, a hybrid wafer or substrate dicing process involving an initial laser scribe and subsequent plasma etch is implemented for die singulation while also removing an oxidation layer from metal bumps on the wafer. In one embodiment, a method includes forming a mask over the semiconductor wafer covering the plurality of ICs, the plurality of ICs including metal bumps or pads with an oxidation layer. The method includes patterning the mask with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the ICs. The method includes plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the plurality of ICs and remove the oxidation layer from the metal bumps or pads.

First claim

What is claimed is:

1. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits (ICs), the method comprising:
forming a mask over the semiconductor wafer covering the plurality of ICs, the plurality of ICs including metal bumps or pads with an oxidation layer;
patterning the mask with a laser scribing process to provide a patterned mask with gaps, removing non-silicon materials and exposing a silicon substrate of the semiconductor wafer between the…

Assignees

• Applied Materials Inc

Inventors

• Lei Wei-Sheng
• Eaton Brad
• Iyer Aparna
• Yalamanchili Madhava Rao
• Kumar Ajay
• Park Jungrae

Classifications

• H10P72/0468

  Electricity · mapped topic

• H10P72/0421

  Electricity · mapped topic

• H10P50/692

  Electricity · mapped topic

• H10P50/691

  Electricity · mapped topic

• H10P50/242

  Electricity · mapped topic