Semiconductor devices and methods of manufacturing thereof
US-2024105795-A1 · Mar 28, 2024 · US
Method of fabricating an interconnection structure in a CMOS comprising a step of forming a dummy electrode
US9105692B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105692-B2 |
| Application number | US-201314058487-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 21, 2013 |
| Priority date | Jul 14, 2010 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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A method for fabricating an interconnection structure in a complementary metal-oxide-semiconductor (CMOS) includes forming an opening in a dielectric layer over a substrate and forming a dummy electrode in a first portion of the opening in the dielectric layer. The method further includes filling a second portion of the opening with a second work-function metal layer, wherein a top surface of the second work-function metal layer is below a top surface of the opening and removing the dummy electrode. The method further includes depositing a first work-function metal layer in the first and second portions, whereby the first work-function metal layer is over the second work-function metal layer in the opening and depositing a signal metal layer over the first work-function metal layer in the first and second portions.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of fabricating an interconnection structure in a complementary metal-oxide-semiconductor (CMOS), comprising: forming an opening in a dielectric layer over a substrate; forming a dummy electrode in a first portion of the opening in the dielectric layer; filling a second portion of the opening with a second work-function metal layer, wherein a top surface of the second work-function metal layer is below a top surface of the opening; removing the…
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Classifications
- H10D64/01318Primary
Electricity · mapped topic
- H10W20/01Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9105692B2 cover?
- A method for fabricating an interconnection structure in a complementary metal-oxide-semiconductor (CMOS) includes forming an opening in a dielectric layer over a substrate and forming a dummy electrode in a first portion of the opening in the dielectric layer. The method further includes filling a second portion of the opening with a second work-function metal layer, wherein a top surface of t…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification H10D64/01318. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).