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Process for manufacturing a semiconductor wafer having SOI-insulated wells and semiconductor wafer thereby manufactured
US9105690B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105690-B2 |
| Application number | US-201113023039-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 8, 2011 |
| Priority date | Jul 17, 2006 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
Official abstract text for this publication.
A process for manufacturing a semiconductor wafer including SOI-insulation wells includes forming, in a die region of a semiconductor body, buried cavities and semiconductor structural elements, which traverse the buried cavities and are distributed in the die region. The process moreover includes the step of oxidizing selectively first adjacent semiconductor structural elements, arranged inside a closed region, and preventing oxidation of second semiconductor structural elements outside the closed region, so as to form a die buried dielectric layer selectively inside the closed region.
First claim
Opening claim text (preview).
The invention claimed is: 1. A semiconductor wafer comprising a semiconductor body including a die region; wherein the semiconductor wafer further comprises: a first epitaxial semiconductor region; a first buried dielectric layer occupying a portion of the die region extending underneath the first epitaxial semiconductor region, said first buried dielectric layer extending to completely surround peripheral side edges of the first epitaxial semiconductor region so as to insulate…
Assignees
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10P90/1906Primary
Electricity · mapped topic
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- What does patent US9105690B2 cover?
- A process for manufacturing a semiconductor wafer including SOI-insulation wells includes forming, in a die region of a semiconductor body, buried cavities and semiconductor structural elements, which traverse the buried cavities and are distributed in the die region. The process moreover includes the step of oxidizing selectively first adjacent semiconductor structural elements, arranged insid…
- Who is the assignee on this patent?
- Barlocchi Gabriele, Corona Pietro, Villa Flavio Francesco, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification H10P90/1906. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).