Device for high voltage applications
US-11862673-B2 · Jan 2, 2024 · US
Isolation structure, semiconductor device having the same, and method for fabricating the isolation structure
US9105684B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105684-B2 |
| Application number | US-201213465593-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 7, 2012 |
| Priority date | Sep 26, 2011 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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An isolation structure of a semiconductor, a semiconductor device having the same, and a method for fabricating the isolation structure are provided. An isolation structure of a semiconductor device may include a trench formed in a substrate, an oxide layer formed on a bottom surface and an inner sidewall of the trench, a filler formed on the oxide layer to fill a part of inside of the trench, and a fourth oxide layer filling an upper portion of the filler of the trench to a height above an upper surface of the trench, an undercut structure being formed on a boundary area between the inner sidewall and the oxide layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for fabricating an isolation structure of a semiconductor device, the method comprising: forming a deep trench by etching a substrate a plurality of times; forming a first oxide layer along an inner side of the deep trench and then annealing the first oxide layer; forming a second oxide layer on the first oxide layer and then annealing the second oxide layer; filling a portion of an inside of the deep trench on the second oxide layer with a fi…
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- H10W10/031Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9105684B2 cover?
- An isolation structure of a semiconductor, a semiconductor device having the same, and a method for fabricating the isolation structure are provided. An isolation structure of a semiconductor device may include a trench formed in a substrate, an oxide layer formed on a bottom surface and an inner sidewall of the trench, a filler formed on the oxide layer to fill a part of inside of the trench, …
- Who is the assignee on this patent?
- Choi Hyung-Suk, Jung Hyun-Tae, Park Eung-Ryul, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification H10W10/031. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).