WH (wafer-holder) process

Patent metadata

Field	Value
Publication number	US-9105675-B2
Application number	US-201313874777-A
Country	US
Kind code	B2
Filing date	May 1, 2013
Priority date	Jan 7, 2004
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

A stacking apparatus that stacks chip assemblies each having a plurality of chips disposed continuously with circuit patterns and electrodes, includes: a plurality of stages each allowed to move arbitrarily, on which the chip assemblies are placed; a storage unit that stores an estimated extent of change in a position of an electrode at each chip, expected to occur as heat is applied to the chip assemblies placed on the plurality of stages during a stacking process; and a control unit that sets positions of the plurality of stages to be assumed relative to each other during the stacking process based upon the estimated extent of change in the position of the electrode at each chip provided from the storage unit and position information indicating positions of individual chips formed at the chip assemblies and controls at least one of the plurality of stages.

First claim

What is claimed is:

1. An apparatus comprising:
a transfer member configured to transfer a plurality of wafers including a first wafer and a second wafer, the first wafer including a first specific area and the second wafer including a second specific area, while the plurality of wafers are held together in alignment such that the first specific area remains aligned with the second specific area,
wherein the alignment of the first specific area and the second specific area allow…

Assignees

• Nikon Corp

Inventors

• Okamoto Kazuya

Classifications

• H10P72/0606

  Electricity · mapped topic

• H10P72/0604

  Electricity · mapped topic

• H10W90/00

  Electricity · mapped topic

• H10P72/50 Primary

  Electricity · mapped topic

• Y10S438/975

  Cross-Sectional Technologies · mapped topic