Metal gates for semiconductor devices and method thereof
US-2024429281-A1 · Dec 26, 2024 · US
Method for enhancing channel strain
US9105664B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105664-B2 |
| Application number | US-201414279689-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 16, 2014 |
| Priority date | May 14, 2010 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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An apparatus includes a substrate having a strained channel region, a dielectric layer over the channel region, first and second conductive layers over the dielectric layer having a characteristic with a first value, and a strain-inducing conductive layer between the conductive layers having the characteristic with a second value different from the first value. A different aspect involves an apparatus that includes a substrate, first and second projections extending from the substrate, the first projection having a tensile-strained first channel region and the second projection having a compression-strained second channel region, and first and second gate structures engaging the first and second projections, respectively. The first gate structure includes a dielectric layer, first and second conductive layers over the dielectric layer, and a strain-inducing conductive layer between the conductive layers. The second gate structure includes a high-k dielectric layer adjacent the second channel region, and a metal layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A method comprising: providing a substrate; forming a projection extending upwardly from the substrate, the projection having a channel region therein; forming a gate structure engaging the projection adjacent to the channel region, the gate structure having spaced first and second conductive layers and a strain-inducing conductive layer disposed between the first and second conductive layers; forming a capping layer over the gate structure; impartin…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9105664B2 cover?
- An apparatus includes a substrate having a strained channel region, a dielectric layer over the channel region, first and second conductive layers over the dielectric layer having a characteristic with a first value, and a strain-inducing conductive layer between the conductive layers having the characteristic with a second value different from the first value. A different aspect involves an ap…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg, Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification H10D84/0167. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).