Techniques providing metal gate devices with multiple barrier layers

Patent metadata

Field	Value
Publication number	US-9105624-B2
Application number	US-201414497639-A
Country	US
Kind code	B2
Filing date	Sep 26, 2014
Priority date	Sep 1, 2011
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.

First claim

What is claimed is:

1. A process of forming a semiconductor device with a metal gate stack, the process comprising:
providing a semiconductor substrate;
depositing a high-k (HK) dielectric layer over the semiconductor substrate;
forming a dummy gate layer over the HK dielectric layer;
removing the dummy gate layer over the HK dielectri layer;
after removing the dummy gate layer overy the HK dielecric layer, depositing a first metal compound barrier layer over the HK dielec…

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Yu xiong-fei
• Chou Chun-Yuan
• Lee Da-Yuan
• Hsu Kuang-Yuan
• Xu Jeff J

Classifications

• H10D84/83135

  Electricity · mapped topic

• H10D64/669

  Electricity · mapped topic

• H10D84/85 Primary

  Electricity · mapped topic

• H10P14/412

  Electricity · mapped topic

• H10P14/44

  Electricity · mapped topic