Spatial semiconductor structure and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9105582-B2
Application number	US-201313968392-A
Country	US
Kind code	B2
Filing date	Aug 15, 2013
Priority date	Aug 15, 2013
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening.

First claim

What is claimed is:

1. A method of fabricating a spatial semiconductor structure, comprising steps as follows:
providing a semiconductor substrate, wherein the semiconductor substrate is made of bulk silicon (Si) substrate, silicon on insulator (SOI), germanium (Ge) substrate or silicon/germanium substrate;
forming a first mask layer above the semiconductor substrate;
forming at least a first opening in the first mask layer and exposing a portion of a surface of the semiconduc…

Assignees

• United Microelectronics Corp

Inventors

• Shih Hung-Lin
• Liu Chih-Chien
• Chen Jei-Ming
• Teng Wen-Yi
• Lo Chieh-Wen

Classifications

• H10P50/691

  Electricity · mapped topic

• H10P14/3411

  Electricity · mapped topic

• H10P14/2905 Primary

  Electricity · mapped topic

• H10P14/271

  Electricity · mapped topic

• H10D84/0193

  Electricity · mapped topic