Interface for metal gate integration

Patent metadata

Field	Value
Publication number	US-9105578-B2
Application number	US-201313836516-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 12, 2013
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

A metal oxide semiconductor field effect transistor (MOSFET) includes a semiconductor substrate and an interlayer dielectric (ILD) over the semiconductor substrate. A gate structure is formed within the ILD and disposed on the semiconductor substrate, wherein the gate structure includes a high-k dielectric material layer and a metal gate stack. One or more portions of a protection layer are formed over the gate stack, and a contact etch stop layer is formed over the ILD and over the one or more portions of the protection layer. The metal gate stack includes aluminum and the protection layer includes aluminum oxide.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, comprising:
forming a metal gate stack over a substrate, wherein the metal gate stack includes a work function metal layer, a blocking layer, and a fill metal layer;
forming a protection layer over the metal gate stack such that the protection layer physically contacts the work function metal layer, the blocking layer, and the fill metal layer, wherein the protection layer is formed by adjusting a pH of a clea…

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Liang Jinn-Kwei
• Sun Chung-Ren
• Jiang Shiu-Ko Jang
• Ko Hsiang-Hsiang

Classifications

• H10P70/277

  Electricity · mapped topic

• H10P14/6314

  Electricity · mapped topic

• H10D64/01316

  Electricity · mapped topic

• H10D64/013

  Electricity · mapped topic

• H10W20/077

  Electricity · mapped topic