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Multi-level memory arrays with memory cells that employ bipolar storage elements and methods of forming the same
US9105576B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105576-B2 |
| Application number | US-201414456158-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 11, 2014 |
| Priority date | Oct 14, 2010 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.
First claim
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The invention claimed is: 1. A memory array comprising: a first memory cell having: a first conductive line; a first bipolar storage element formed above the first conductive line; a second conductive line formed above the first bipolar storage element; and a first steering element disposed above or below the first bipolar storage element; and a second memory cell formed above the first memory cell, the second memory cell having: a third conductive line; a second bip…
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Electricity · mapped topic
Electricity · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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- What does patent US9105576B2 cover?
- In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed…
- Who is the assignee on this patent?
- Sandisk 3D Llc
- What technology area does this patent fall under?
- Primary CPC classification G11C13/0007. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).