High voltage depletion mode N-channel JFET
US-9202692-B2 · Dec 1, 2015 · US
Monolithic integrated composite group III-V and group IV device
US9105566B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105566-B2 |
| Application number | US-201313968840-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 16, 2013 |
| Priority date | Dec 10, 2009 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a sidewall of the trench.
First claim
Opening claim text (preview).
The invention claimed is: 1. A monolithic integrated composite device comprising: a group IV semiconductor body formed in a trench in a group III-V semiconductor body situated over a group IV semiconductor substrate, said group IV semiconductor body including first and second defective regions adjacent to respective first and second sidewalls of said trench; and at least one passive device fabricated in at least one of said first and said second defective regions.…
Assignees
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D84/0123Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9105566B2 cover?
- According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in the…
- Who is the assignee on this patent?
- Int Rectifier Corp
- What technology area does this patent fall under?
- Primary CPC classification H10D84/0123. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).