Method of making metal substrates with structures formed therein
US-2024404922-A1 · Dec 5, 2024 · US
Package on package devices and methods of packaging semiconductor dies
US9105552B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105552-B2 |
| Application number | US-201213483734-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 30, 2012 |
| Priority date | Oct 31, 2011 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal stud bumps are disposed between the first packaged die and the second packaged die. The metal stud bumps include a bump region and a tail region coupled to the bump region. The metal stud bumps are embedded in solder joints.
First claim
Opening claim text (preview).
What is claimed is: 1. A package-on-package (PoP) device, comprising: a first packaged die comprising a first die; a second packaged die comprising a second die coupled to the first packaged die; and a plurality of metal stud bumps disposed between the first packaged die and the second packaged die, wherein the plurality of metal stud bumps is disposed laterally adjacent to the first die of the first packaged die, and wherein the plurality of metal stud bumps each include a bu…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9105552B2 cover?
- Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal stud bumps are disposed between the first packaged die and the second packaged die. The metal stud bumps include a bump region and a tail region coupled to the bump region. The metal stud bumps a…
- Who is the assignee on this patent?
- Yu Chen-Hua, Lee Chien-Hsiun, Ching Chen Yung, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification H10W70/698. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).