Solid-state imaging device and manufacturing method of the same, and electronic apparatus

US9105539B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9105539-B2
Application numberUS-201314372413-A
CountryUS
Kind codeB2
Filing dateJan 11, 2013
Priority dateJan 23, 2012
Publication dateAug 11, 2015
Grant dateAug 11, 2015

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

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The present disclosure relates to a solid-state imaging device and a manufacturing method of the same, and an electronic apparatus, capable of more reliably suppressing occurrence of color mixing. A trench is formed between PDs so as to be opened to a light receiving surface side of a semiconductor substrate on which a plurality of the PDs, each of which receives light to generate charges, are formed, an insulating film is embedded in the trench and the insulating film is laminated on a back surface side of the semiconductor substrate. Then, a light shielding portion is formed so as to be laminated on the insulating film and to have a convex shape protruding to the semiconductor substrate at a location corresponding to the trench. The present technology can be applied to a back surface irradiation type CMOS solid-state imaging device.

First claim

Opening claim text (preview).

What is claimed is: 1. A solid-state imaging device comprising: a semiconductor substrate on which a plurality of photoelectric conversion units, each of which receives light to generate charges, are formed; a recessed portion that is formed between the photoelectric conversion units so as to be opened to a light receiving surface side of the semiconductor substrate; an insulating film which is embedded in the recessed portion and laminated on the back surface side of the semi…

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What does patent US9105539B2 cover?
The present disclosure relates to a solid-state imaging device and a manufacturing method of the same, and an electronic apparatus, capable of more reliably suppressing occurrence of color mixing. A trench is formed between PDs so as to be opened to a light receiving surface side of a semiconductor substrate on which a plurality of the PDs, each of which receives light to generate charges…
Who is the assignee on this patent?
Sony Corp
What technology area does this patent fall under?
Primary CPC classification H10F39/8057. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).