Display panel structure of electrophoretic display device with flat protection layer over active region and protection circuit region

US9105528B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9105528-B2
Application numberUS-201113106882-A
CountryUS
Kind codeB2
Filing dateMay 13, 2011
Priority dateDec 15, 2010
Publication dateAug 11, 2015
Grant dateAug 11, 2015

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  2. Abstract

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  5. First independent claim

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Abstract

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A display device structure includes a substrate having an active region and an electrostatic protection circuit region. The first metal layer, the first insulation layer, and an amorphous silicon layer are sequentially disposed on the substrate; the first opening passes through the first insulation layer for exposing part of the first metal layer. The second metal layer, disposed on the first insulation layer or the amorphous silicon layer, fills the first opening to contact with the first metal layer; the second insulation layer and the flat layer are disposed on the second metal layer, in which the region of the flat layer overlaps the electrostatic protection circuit region. The second opening passes through the second insulation layer and the flat layer for exposing the second metal layer, in which the third metal layer fills the second opening to contact with the second metal layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A display device structure, comprising: a substrate comprising an active region and an electrostatic protection circuit region adjacent to the active region; a first metal layer disposed in the active region and the electrostatic protection circuit region; a first insulation layer disposed on the first metal layer in the active region and the electrostatic protection circuit region, wherein the first insulation layer has a first opening positioned in the…

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What does patent US9105528B2 cover?
A display device structure includes a substrate having an active region and an electrostatic protection circuit region. The first metal layer, the first insulation layer, and an amorphous silicon layer are sequentially disposed on the substrate; the first opening passes through the first insulation layer for exposing part of the first metal layer. The second metal layer, disposed on the first i…
Who is the assignee on this patent?
Liu Chuan-Feng, E Ink Holdings Inc
What technology area does this patent fall under?
Primary CPC classification H10D86/0231. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).