Memory device and method for writing therefor

Patent metadata

Field	Value
Publication number	US-9105326-B2
Application number	US-201414291162-A
Country	US
Kind code	B2
Filing date	May 30, 2014
Priority date	Jul 30, 2012
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

A method of writing a memory cell includes, during a write cycle, causing a voltage level at a power terminal of the memory cell to change from a supply voltage level toward a first voltage level. The voltage level at the power terminal of the memory cell is maintained at the first voltage level for a first predetermined duration. The voltage level at the power terminal of the memory cell is maintained at a second voltage level for a second predetermined duration, where the second voltage level is between the first voltage level and the supply voltage level. During the write cycle, the voltage level at the power terminal of the memory cell is caused to change from the first voltage level toward the supply voltage level.

First claim

What is claimed is:

1. A method of writing a memory cell, comprising:
during a write cycle:
causing a voltage level at a power terminal of the memory cell to change from a supply voltage level toward a first voltage level;
maintaining the voltage level at the power terminal of the memory cell at the first voltage level for a first predetermined duration;
maintaining the voltage level at the power terminal of the memory cell at a second voltage level for a second predetermined…

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Chen Yen-Huei
• Wang Li-Wen
• Lin Chih-Yu

Classifications

• G11C7/22 Primary

  Physics · mapped topic

• G11C11/419

  Physics · mapped topic

• G11C7/12 Primary

  Physics · mapped topic